LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 27

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BANK 0
BANK1
SMSC LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
BYTE
BYTE
HIGH
LOW
BYTE
BYTE
OFFSET
HIGH
LOW
MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve
memory to be used later for transmit, limiting the amount of memory that receive packets can use. When
programmed for zero, the memory allocation between transmit and receive is completely dynamic. When
programmed for a non-zero value, the allocation is dynamic if the free memory exceeds the programmed
value, while receive allocation requests are denied if the free memory is less or equal to the programmed
value. This register defaults to zero upon reset. It is not affected by the RESET MMU command.
The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY
CURRENTLY IN USE. If the memory allocated for transmit plus the reserved space for transmit is required
to be constant (rather than grow with transmit allocations) the CPU should update the value of this register
after allocating or releasing memory.
The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where
M is the Memory Size Multiplier. M=2 for the LAN91C100FD. A value of 04h in the lower byte of the MCR
is equal to one 2K page (4 * 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0
and 1 of the MCR should be written to 1 only when the entire memory is being reserved for transmit (i.e.,
low byte of MCR = FFh).
The Configuration Register holds bits that define the adapter configuration and are not expected to change
during run-time. This register is part of the EEPROM saved setup.
MII SELECT - Used to select the network interface port. When set, the LAN91C100FD will use its MII port
and interface a PHY device at the nibble rate. When clear, the LAN91C100FD will use its 10 Mbps ENDEC
interface. This bit drives the MII SEL pin. Switching between ports should be done with transmitter and
receiver disabled and no transmit/receive packets in progress.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the
Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three clocks on any
cycle to the LAN91C100FD.
OFFSET
0
A
SELECT
MII
1
1
1
0
0
CONFIGURATION REGISTER
CONFIGURATION
0
0
0
MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M)
0
0
REGISTER
MEMORY
NAME
NAME
1
1
1
0
DATASHEET
Reserved
Page 27
WAIT
NO
1
0
0
1
Lower Byte - READ/WRITE
Upper Byte - READ ONLY
MEMORY SIZE MULTIPLIER
READ/WRITE
0
0
TYPE
0
0
TYPE
STEP
1
0
FULL
SEL1
INT
0
0
0
0
SEL0
INT
SYMBOL
SYMBOL
0
0
0
MCR
CR
Revision 1.0 (09-22-08)
1
0
SELECT
AUI
0
1