LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 60

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4
Revision 1.0 (09-22-08)
combined with
combined with
Latched W-R
Latched W-R
nBE0 nBE1
nBE2 nBE3
EISA 32 Bit SLAVEEISA 32 Bit Slave
On EISA the LAN91C100FD is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path
option. As an I/O slave, the LAN91C100FD uses asynchronous accesses. In creating nRD and nWR
inputs, the timing information is externally derived from nCMD edges. Given that the access will be at least
1.5 to 2 clocks (more than 180ns at least) there is no need to negate EXRDY, simplifying the EISA
interface implementation. As a DMA Slave, the LAN91C100FD accepts burst transfers and is able to
sustain the peak rate of one doubleword every BCLK. Doubleword alignment is assumed for DMA
transfers. Up to three extra bytes in the beginning and at the end of the transfer should be moved by the
CPU using I/O accesses to the Data Register. The LAN91C100FD will sample EXRDY and postpone DMA
cycles if the memory cycle solicits wait states.
EISA BUS
LA2-LA15
RESDRV
SIGNAL
nSTART
D0-D31
M/nIO
nCMD
nCMD
IRQn
AEN
LAN91C100FD
INTR0-INTR3
nBE0 n BE1
nBE2 nBE3
SIGNAL
D0-D31
A2-A15
RESET
Table 7.3 - EISA 32 Bit Slave Signal Connections
nADS
nWR
AEN
nRD
Address bus used for I/O space and register decoding,
latched by nADS (nSTART) trailing edge.
Qualifies valid I/O decoding - enabled access when low.
These signals are externally ORed. Internally the AEN pin is
latched by nADS rising edge and transparent while nADS is
low.
I/O Read strobe - asynchronous read accesses. Address is
valid before its leading edge. Must not be active during DMA
bursts if DMA is supported.
I/O Write strobe - asynchronous write access. Address is
valid before leading edge . Data latched on trailing edge.
Must not be active during DMA bursts if DMA is supported.
Address strobe is connected to EISA nSTART.
Byte enables. Latched on nADS rising edge.
Interrupts used as active high edge triggered
32 bit data bus. The bus byte(s) used to access the device
are a function of nBE0-nBE3:
nBE0
Not used = tri-state on reads, ignored on writes. Note that
nBE2 and nBE3 override the value of A1, which is tied low in
this application. Other combinations of nBE are not
supported by the LAN91C100FD. Software drivers are not
anticipated to generate them.
DATASHEET
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0
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0
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Page 60
nBE1 nBE2
0
0
1
1
0
1
1
0
1
0
1
1
0
1
FEAST Fast Ethernet Controller with Full Duplex Capability
NOTES
nBE3
0
1
0
1
1
1
0
Double word access
Low word access
High word access
Byte 0 access
Byte 1 access
Byte 2 access
Byte 3 access
SMSC LAN91C100FD Rev. D