LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 24

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BANK 0
Revision 1.0 (09-22-08)
BYTE
BYTE
HIGH
LOW
OFFSET
LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY
chip in loopback mode.
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the
LAN91C100FD will complete the current transmission before stopping. When stopping due to an error, this
bit is automatically cleared.
This register stores the status of the last transmitted frame. This register value, upon individual transmit
packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt
processing should use the copy in memory as the register itself will be updated by subsequent packet
transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is
cleared the register holds the last packet completion status.
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A
transition on the value of this bit generates an interrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15).
Cleared by reading the ECR register.
EXC_DEF - Excessive Deferral. When set last/ current transmit was deferred for more than 1518 * 2 byte
times. Cleared at the end of every packet sent.
LOST_CARR - Lost Carrier Sense. When set indicates that Carrier Sense was not present at end of
preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.
Cleared by setting TXENA bit in TCR.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64
byte times into the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit
in TCR. Cleared by setting TXENA in TCR.
TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 μs of the inter frame
gap. Cleared at the end of every packet sent.
LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every
transmit frame.
SQET - Signal Quality Error Test. In MII, SQET bit is always set after first transmit, except if SWFDUP=1.
As a consequence, the STP_SQET bit in the TCR register cannot be set as it will always result in transmit
fatal error. In non-MII systems, the transmitter opens a 1.6 μs window 0.8 μs after transmission is
completed and the receiver returns inactive. During this window, the transmitter expects to see the SQET
signal from the transceiver. The absence of this signal is a 'Signal Quality Error' and is reported in this
status bit. Transmission stops and EPH INT is set if STP_SQET is in the TCR is also set when SQET is
set. This bit is cleared by setting TXENA high.
2
Reserved
DEFR
TX
0
0
EPH STATUS REGISTER
-nLNK
LINK_
BRD
LTX
OK
pin
0
NAME
SQET
0
0
0
DATASHEET
16COL
Page 24
_ROL
CTR
0
0
READ ONLY
TYPE
MULT
_DEF
EXC
LTX
0
0
FEAST Fast Ethernet Controller with Full Duplex Capability
CARR
LOST
MUL
COL
0
0
LATCOL
SYMBOL
EPHSR
SNGL
SMSC LAN91C100FD Rev. D
COL
0
0
TX_SUC
0
0
0