LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 8

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.0 (09-22-08)
PQFP/TQFP
13, 15, 16
PIN NO.
187-189
176,
175
106
109
108
177
178
190
54
55
52
53
51
Asynchron-
ous Ready
nSynchron
-
ous Ready
nReady
Return
Interrupt
nLocal
Device
nRead
Strobe
nWrite
Strobe
nData
Path Chip
Select
EEPROM
Clock
EEPROM
Select
EEPROM
Data Out
EEPROM
Data In
I/O Base
Enable
EEPROM
NAME
ARDY
nSRDY
nRDYRTN
INTR0-
INTR3
nLDEV
nRD
nWR
nDATACS
EESK
EECS
EEDO
EEDI
IOS0-
IOS2
ENEEP
SYMBOL
DATASHEET
BUFFER
pulldown
pullup
pullup
pullup
TYPE
OD16
I with
I with
I with
I with
O16
O24
O16
O4
O4
O4
IS
IS
I
Page 8
Open drain output. ARDY may be used when
interfacing asynchronous buses to extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
Output. This output is used when interfacing
synchronous buses and nVLBUS=0 to extend
accesses. This signal remains normally inactive,
and its falling edge indicates completion. This
signal is synchronous to the bus clock LCLK.
Input. This input is used to complete
synchronous read cycles. In EISA burst mode it
is sampled on falling LCLK edges, and
synchronous cycles are delayed until it is
sampled high.
Outputs. Only one of these interrupts is selected
to be used; the other three are tri-stated. The
selection is determined by the value of INT SEL
1-0 bits in the Configuration Register.
Output. This active low output is asserted when
AEN is low and A4-A15 decode to the
LAN91C100FD address programmed into the
high byte of the Base Address Register. nLDEV
is a combinatorial decode of unlatched address
and AEN signals.
Input. Used in asynchronous bus interfaces.
Input. Used in asynchronous bus interfaces.
Input. When nDATACS is low, the Data Path
can be accessed regardless of the values of
AEN, A1-A15 and the content of the BANK
SELECT Register. nDATACS provides an
interface for bursting to and from the
LAN91C100FD 32 bits at a time.
Output. 4 μsec clock used to shift data in and
out of the serial EEPROM.
Output. Serial EEPROM chip select. Used for
selection and command framing of the serial
EEPROM.
Output. Connected to the DI input of the serial
EEPROM.
Input. Connected to the DO output of the serial
EEPROM.
Input. External switches can be connected to
these lines to select between predefined
EEPROM configurations.
Input. Enables (when high or open)
LAN91C100FD accesses to the serial EEPROM.
Must be grounded if no EEPROM is connected
to the LAN91C100FD.
FEAST Fast Ethernet Controller with Full Duplex Capability
DESCRIPTION
SMSC LAN91C100FD Rev. D