LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 7

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3
SMSC LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
PQFP/TQFP
164, 144,
127, 126,
124, 123,
121, 118,
173-170,
168-166,
142-139,
137-135,
131-129,
115-112,
PIN NO.
148-159
145-147
160-163
133,
117,
193
110
182
183
184
181
105
95
Address
Address
Address
Enable
nByte
Enable
Data Bus
Reset
nAddress
Strobe
nCycle
Write/
nRead
nVL Bus
Access
Local Bus
Clock
NAME
Description of Pin Functions
A4-A15
A1-A3
AEN
nBE0-
nBE3
D0-D31
RESET
nADS
nCYCLE
W/nR
nVLBUS
LCLK
SYMBOL
DATASHEET
BUFFER
pullup
TYPE
I/O24
I with
IS
IS
IS
I
I
I
I
I
I
Page 7
Input. Decoded by LAN91C100FD to determine
access to its registers.
Input. Used by LAN91C100FD for internal
register selection.
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
Input. Used during LAN91C100FD register
accesses to determine the width of the access
and the register(s) being accessed. nBE0-nBE3
are ignored when nDATACS is low (burst
accesses) because 32 bit transfers are
assumed.
Bidirectional. 32 bit data bus used to access the
LAN91C100FD’s internal registers. Data bus
has weak internal pullups. Supports direct
connection to the system bus without external
buffering. For 16 bit systems, only D0-D15 are
used.
Input. This input is not considered active unless
it is active for at least 100ns to filter narrow
glitches.
Input. For systems that require address latching,
the rising edge of nADS indicates the latching
moment for A1-A15 and AEN. All
LAN91C100FD internal functions of A1-A15,
AEN are latched except for nLDEV decoding.
Input. This active low signal is used to control
LAN91C100FD EISA burst mode synchronous
bus cycles.
Input. Defines the direction of synchronous
cycles. Write cycles when high, read cycles
when low.
Input. When low, the LAN91C100FD
synchronous bus interface is configured for VL
Bus accesses. Otherwise, the LAN91C100FD is
configured for EISA DMA burst accesses. Does
not affect the asynchronous bus interface.
Input. Used to interface synchronous buses.
Maximum frequency is 50 MHz. Limited to 8.33
MHz for EISA DMA burst mode.
DESCRIPTION
Revision 1.0 (09-22-08)