LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 20

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RECEIVE FRAME STATUS WORDRECEIVE FRAME STATUS WORD
Revision 1.0 (09-22-08)
BYTE
BYTE
HIGH
LOW
The transmit byte count least significant bit will be assumed 0 by the controller regardless of the value
written in memory.
DATA AREA - The data area starts at offset 4 of the packet structure and can extend up to 2043 bytes.
The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE
ADDRESS, followed by a variable-length number of bytes. On transmit, all bytes are provided by the
CPU, including the source address. The LAN91C100FD does not insert its own source address. On
receive, all bytes are provided by the CSMA side.
The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C100FD. It is
treated transparently as data both for transmit and receive operations.
CONTROL BYTE - For transmit packets the CONTROL BYTE is written by the CPU as:
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE.
If clear, the number of data bytes is even and the byte before the CONTROL BYTE is not transmitted.
CRC - When set, CRC will be appended to the frame. This bit has only meaning if the NOCRC bit in the
TCR is set.
For receive packets the CONTROL BYTE is written by the controller as:
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE.
If clear, the number of data bytes is even and the byte before the CONTROL BYTE should be ignored.
This word is written at the beginning of each receive frame in memory. It is not available as a register.
ALGN
ERR
X
0
BROD
CAST
X
1
5
ODD
ODD
BAD
CRC
4
DATASHEET
CRC
0
Page 20
ODD
FRM
HASH VALUE
3
0
0
TOOLNG
2
FEAST Fast Ethernet Controller with Full Duplex Capability
0
0
SHORT
TOO
1
0
0
SMSC LAN91C100FD Rev. D
0
0
0
MULT
CAST