LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 110

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
8.4.8
D[31:0] (INPUT)
PIO Writes
PIO writes are used for all LAN9312 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle
ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must
de-assert between cycles for the period specified in
page
must be de-asserted between cycles for the period specified. The PIO write cycle is illustrated in the
functional timing diagram in
The END_SEL signal has the same timing characteristics as the address lines.
Please refer to
for PIO write operations.
nCS, nWR
END_SEL
449. They may be asserted and de-asserted in any order. Either or both of these control signals
A[x:2]
Figure 8.7 Functional Timing for PIO Write Operation
Section 15.5.8, "PIO Write Cycle Timing," on page 449
Figure
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
8.7.
110
VALID
VALID
Table 15.12, “PIO Write Cycle Timing Values,” on
VALID
for the AC timing specifications
SMSC LAN9312
Datasheet