LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 98

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
7.3.1.3
7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
Virtual PHY Pause Flow Control
The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHYs
advertised pause flow control abilities are set via bits 10 (Symmetric Pause) and 11 (Asymmetric
Pause) of the
Virtual PHY to advertise its flow control abilities and auto-negotiate the flow control settings with the
emulated link partner. The default values of these bits are as shown in
Auto-Negotiation Advertisement Register (VPHY_AN_ADV)," on page
The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised
pause flow control abilities of the Virtual PHY in (bits 10 & 11) of the
Advertisement Register
asymmetric/symmetric pause ability settings requested by the Virtual PHY, as shown in
“Emulated Link Partner Pause Flow Control Ability Default Values,” on page
The pause flow control settings may also be manually set via the
Control Register
to be manually set when auto-negotiation is disabled or the Manual Flow Control Select bit 0 is set.
The currently enabled duplex and flow control settings can also be monitored via this register. The flow
control values in the
affected by the values of the manual flow control register. Refer to
Logic," on page 58
Virtual PHY Resets
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY
supports three block specific resets. These are is discussed in the following sections. For detailed
information on all LAN9312 resets, refer to
Virtual PHY Software Reset via RESET_CTL
The Virtual PHY can be reset via the
(VPHY_RST). This bit is self clearing after approximately 102uS.
Virtual PHY Software Reset via VPHY_BASIC_CTRL
The Virtual PHY can also be reset by setting bit 15 (VPHY_RST) of the
Register
Virtual PHY Software Reset via PMT_CTRL
The Virtual PHY can be reset via the
10 (VPHY_RST). This bit is self clearing after approximately 102uS.
(VPHY_BASIC_CTRL). This bit is self clearing and will return to 0 after the reset is complete.
Virtual PHY Auto-Negotiation Advertisement Register
(MANUAL_FC_MII). This register allows the switch fabric port 0 flow control settings
for additional information.
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)
(VPHY_AN_ADV). Thus, the emulated link partner always accommodates the
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
Power Management Control Register (PMT_CTRL)
Reset Control Register (RESET_CTL)
98
Section 4.2, "Resets," on page
Section 6.2.3, "Flow Control Enable
(VPHY_AN_ADV). This allows the
Port 0(Host MAC) Manual Flow
252.
Section 14.2.8.5, "Virtual PHY
Virtual PHY Auto-Negotiation
36.
Virtual PHY Basic Control
255.
by setting bit 3
SMSC LAN9312
by setting bit
Table 14.5,
Datasheet
are not