LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 300

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
14.4.2.9
MODE[2:0]
BITS
15:8
7:5
4:0
000
001
010
RESERVED
PHY Mode (MODE[2:0])
This field controls the PHY mode of operation. Refer to
definition of each mode.
PHY Address (PHYADD)
The PHY Address field determines the MMI address to which the PHY will
respond and is also used for initialization of the cipher (scrambler) key. Each
PHY must have a unique address. Refer to
Addressing," on page 82
Note:
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
This read/write register is used to control the special modes of the Port x PHY.
Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD
Note 14.58 Register bits designated as NASR are reset when the Port x PHY Reset is generated via
Note 14.59 The default value of this field is determined by a combination of the configuration straps
Note 14.60 The default value of this field is determined by the phy_addr_sel_strap configuration strap.
10BASE-T Half Duplex. Auto-negotiation disabled.
10BASE-T Full Duplex. Auto-negotiation disabled.
100BASE-TX Half Duplex. Auto-negotiation
disabled. CRS is active during Transmit & Receive.
No check is performed to ensure that this address is unique from
the other PHY addresses (Port 1 PHY, Port 2 PHY, and Virtual
PHY).
command. Refer to
Index (decimal): 18
the
t h e
(PHY_BASIC_CONTROL_x)
autoneg_strap_x, speed_strap_x, and duplex_strap_x. If the autoneg_strap_x is 1, then
the default MODE[2:0] value is 111b. Else, the default value of this field is determined by
the remaining straps. MODE[2]=0, MODE[1]=(speed_strap_1 for Port 1 PHY,
speed_strap_2 for Port 2 PHY), and MODE[0]=(duplex_strap_1 for Port 1 PHY,
duplex_strap_2 for Port 2 PHY). Configuration strap values are latched upon the de-
assertion of a chip-level reset as described in
page
definitions.
Refer to
Reset Control Register
MODE DEFINITIONS
R e s e t ( P H Y _ R S T )
40. Refer to
Section 7.1.1, "PHY Addressing," on page 82
for additional information.
Table 14.10 MODE[2:0] Definitions
DESCRIPTION
Section 10.2.4, "EEPROM Loader," on page 149
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Section 4.2.4, "Configuration Straps," on page 40
DATASHEET
(RESET_CTL). The NASR designation is only applicable when
is set.
Section 7.1.1, "PHY
b i t o f t h e
300
Size:
Table 14.10
P o r t x P H Y B a s i c C o n t r o l R e g i s t e r
PHY_BASIC_CONTROL_x
AFFECTED REGISTER BIT VALUES
Section 4.2.4, "Configuration Straps," on
[13,12,10,8]
16 bits
0000
0001
1000
for a
for additional information.
Note 14.58
Note 14.58
NASR
NASR
TYPE
for more information.
R/W
R/W
RO
for configuration strap
PHY_AN_ADV_x
[8,7,6,5]
SMSC LAN9312
DEFAULT
N/A
N/A
N/A
Note 14.59
Note 14.60
Datasheet
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