LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 111

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
8.4.9
8.5
D[31:0] (INPUT)
TX Data FIFO Direct PIO Writes
In this mode only A[2] is decoded, and any write to the LAN9312 will write the TX Data FIFO. This
mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished
by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host
processor must increment its address when accessing the LAN9312.
Timing is identical to a PIO write, and the FIFO_SEL and END_SEL signals have the same timing
characteristics as the address lines. A TX Data FIFO direct PIO write cycle begins when both nCS and
nWR are asserted. Either or both of these control signals must de-assert between cycles for the period
specified in
ends when either or both nCS and nWR are de-asserted. They may be asserted and de-asserted in
any order. The TX Data FIFO direct PIO write cycle is illustrated in the functional timing diagram in
Figure
Note:
Please refer to
timing specifications for TX Data FIFO direct PIO write operations.
The HBI allows access to all interrupt configuration and status registers within the LAN9312. The
LAN9312 implements a multi-tier interrupt hierarchy with the
(IRQ_CFG),
level. These registers allow for the configuration of which interrupts trigger the IRQ, as well as the IRQ
deassertion and polarity properties. Interrupts may be generated from the 1588 Timestamping, Switch
Fabric, Port 1 PHY, Port 2 PHY, Host MAC, EEPROM Loader, General Purpose Timer, General
Purpose I/O, and Power Management blocks.
For more information of the LAN9312 interrupts, refer to
HBI Interrupts
Figure 8.8 Functional Timing for TX Data FIFO Direct PIO Write Operation
nCS, nWR
END_SEL
FIFO_SEL
8.8.
A[9:3] are ignored during TX Data FIFO direct PIO writes.
A[x:3]
Table 15.13, “TX Data FIFO Direct PIO Write Cycle Timing Values,” on page
A[2]
Interrupt Status Register
Section 15.5.9, "TX Data FIFO Direct PIO Write Cycle Timing," on page 450
(WRITE DATA TO TX DATA FIFO)
DATASHEET
(INT_STS), and
111
VALID
VALID
Interrupt Enable Register (INT_EN)
Chapter 5, System
VALID
Interrupt Configuration Register
Interrupts.
Revision 1.7 (06-29-10)
450. The cycle
for the AC
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