LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 251
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LAN9312-NZW
Manufacturer Part Number
LAN9312-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NZW.pdf
(458 pages)
Specifications of LAN9312-NZW
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.8.4
31:16
15:10
BITS
9:4
3:0
RESERVED
(See
PHY ID
This field contains the lower 6-bits of the Virtual PHY OUI
Model Number
This field contains the 6-bit manufacturer’s model number of the Virtual PHY
(Note
Revision Number
This field contain the 4-bit manufacturer’s revision number of the Virtual PHY
(Note
Virtual PHY Identification LSB Register (VPHY_ID_LSB)
This read/write register contains the LSB of the Virtual PHY Organizationally Unique Identifier (OUI).
The MSB of the Virtual PHY OUI is contained in the
(VPHY_ID_MSB).
Note 14.25 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 14.26 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.
Note
14.26).
14.26).
14.25)
Offset:
Index (decimal):
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
1CCh
3
DESCRIPTION
DATASHEET
251
Size:
(Note
Virtual PHY Identification MSB Register
14.26).
32 bits
TYPE
R/W
R/W
R/W
RO
Revision 1.7 (06-29-10)
DEFAULT
000000b
000000b
0000b
-
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