LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 48
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LAN9312-NZW
Manufacturer Part Number
LAN9312-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NZW.pdf
(458 pages)
Specifications of LAN9312-NZW
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Revision 1.7 (06-29-10)
4.3.2
The Port 1 & 2 PHY energy-detect events are capable of asserting the PME output by additionally
setting the PME_EN and ED_EN2 (Port 2 PHY) or ED_EN1 (Port 1 PHY) bits of the
Management Control Register
Host MAC Power Management
The Host MAC provides wake-up frame and magic packet detection modes. When enabled in the
MAC Wake-up Control and Status Register (HMAC_WUCSR)
and the MPEN bit for magic packets), detection of wake-up frames or magic packets causes the WUFR
and MPR bits of the HMAC_WUCSR register to set, respectively. If either of the WUFR and MPR bits
are set, the WOL_STS bit of the
events can enable PME output assertion by additionally setting the PME_EN bit of the
Management Control Register
The IRQ interrupt output can be triggered by a wake-up frame or magic packet as described in
5.2.6, "Power Management Interrupts," on page
Refer to
Detection," on page 118
Section 9.5, "Wake-up Frame Detection," on page 116
for additional details on these features.
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
(PMT_CTRL).
(PMT_CTRL).
Power Management Control Register (PMT_CTRL)
DATASHEET
48
53.
(via the WUEN bit for wake-up frames,
and
Section 9.5.1, "Magic Packet
will be set. These
SMSC LAN9312
Datasheet
Section
Power
Power
Host
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