LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 247
LAN9312-NZW
Manufacturer Part Number
LAN9312-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NZW.pdf
(458 pages)
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
BITS
5:0
7
6
Collision Test (VPHY_COL_TEST)
This bit enables/disables the collision test mode. When set, the collision
signal to the Host MAC is active during transmission from the Host MAC.
Note:
0: Collision test mode disabled
1: Collision test mode enabled
Speed Select MSB (VPHY_SPEED_SEL_MSB)
This bit is not used by the Virtual PHY and has no effect. The value returned
is always 0.
RESERVED
Note 14.16 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
It is recommended that this bit be used only when in loopback
mode.
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
DESCRIPTION
DATASHEET
247
TYPE
R/W
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
-
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