LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 364

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
14.5.2.43
BITS
31:8
7:0
RESERVED
RESERVED
Note:
Port x MAC Interrupt Mask Register (MAC_IMR_x)
This register contains the Port x interrupt mask. Port x related interrupts in the
Pending Register (MAC_IPR_x)
corresponding bit of this register. Clearing a bit will unmask the interrupt. Refer to
Interrupts," on page 49
Note: There are no possible Port x interrupt conditions available. This register exists for future use,
These bits must be written as 11h
and should be configured as indicated for future compatibility.
Register #:
for more information.
Port0: 0480h
Port1: 0880h
Port2: 0C80h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
may be masked via this register. An interrupt is masked by setting the
DATASHEET
364
Size:
32 bits
TYPE
R/W
RO
Port x MAC Interrupt
Chapter 5, "System
SMSC LAN9312
DEFAULT
11h
Datasheet
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