LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 379
LAN9312-NZW
Manufacturer Part Number
LAN9312-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NZW.pdf
(458 pages)
Specifications of LAN9312-NZW
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.5.3.12
BITS
31:8
5:0
7
6
RESERVED
DIFFSERV Table RnW
This bit specifies a read(1) or a write(0) command.
RESERVED
DIFFSERV Table Index
This field specifies the ToS/CS entry that is accessed.
Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)
This register is used to read and write the DIFFSERV table. A write to this address performs the
specified access. This table is used to map the received IP ToS/CS to a priority.
For a read access, the Operation Pending bit in the
Register (SWE_DIFFSERV_TBL_CMD_STS)
Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA)
F o r a w r i t e a c c e s s , t h e
(SWE_DIFFSERV_TBL_WR_DATA)
Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)
indicates when the command is finished.
Register #:
1811h
DESCRIPTION
S w i t c h E n g i n e D I F F S E R V Ta b l e W r i t e D a t a R e g i s t e r
DATASHEET
register should be written first. The Operation Pending bit in the
379
indicates when the command is finished. The
Size:
Switch Engine DIFFSERV Table Command Status
32 bits
TYPE
R/W
R/W
RO
RO
Revision 1.7 (06-29-10)
can then be read.
DEFAULT
0b
0h
-
-
Switch
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