PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 142

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

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The buffer functions are:
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Controlled by special signals generated by the receiver, the unipolar bit stream is
converted into bit-parallel, time slot serial data which is circularly written to the elastic
buffer using internally generated Receive Route Clock (RCLK).
Reading of stored data is controlled by the system clock sourced by SCLKR or by the
receive jitter attenuator and the synchronization pulse (SYPR) together with the
programmed offset values for the receive time slot/clock slot counters. After conversion
into a serial data stream, the data is sent out on port RDO. If the receive buffer is
bypassed programming of the time slot offset is disabled and data is clocked off with
RCLK instead of SCLKR.
The 24 received time slots (T1/J1) can be translated into the 32 system time slots (E1)
in two different channel translation modes (FMR1.CTM). Unequipped time slots are set
to FF
Data Sheet
RBS1/0 = 00: two frame buffer or 386 bits
Maximum of wander amplitude (peak-to-peak): (1 UI = 648 ns)
System interface clocking rate: modulo 2.048 MHz:
142 UI in channel translation mode 0
78 UI in channel translation mode 1
System interface clocking rate: modulo 1.544 MHz:
Maximum of wander: 140 UI
average delay after performing a slip: 1 frame or 193 bits
RBS1/0 = 01: one frame buffer or 193 bits
System interface clocking rate: modulo 2.048 MHz:
Maximum of wander: 70 UI in channel translation mode 0
Maximum of wander: 50 UI in channel translation mode 1
System interface clocking rate: modulo 1.544 MHz:
Maximum of wander: 74 UI
average delay after performing a slip: 96 bits
RBS1/0 = 10: short buffer or 96 bits
System interface clocking rate: modulo 2.048 MHz:
Maximum of wander: 28 UI in channel translation mode 0; channel translation mode
1 not supported
System interface clocking rate: modulo 1.544 MHz:
Maximum of wander: 38 UI
average delay after performing a slip: 48 bits
RBS1/0 = 11: Bypass of the receive elastic buffer
Clock adaption between system clock (SCLKR) and internally generated route clock
(RCLK).
Compensation of input wander and jitter.
Frame alignment between system frame and receive route frame
Reporting and controlling of slips
H
. See
Table
33.
142
Functional Description T1/J1
Rev. 1.1, 2005-06-13
PEF 2256 H/E
FALC
®
56