PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 360

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

HDLCI
Receive Address Byte High Register 1 (Read/Write)
Value after reset: FD
RAH1
In operating modes that provide high byte address recognition, the high byte of the
received address is compared to the individually programmable values in RAH1 and
RAH2. The address registers are used by all HDLC channels in common.
RAH1
Receive Address Byte High Register 2 (Read/Write)
Value after reset: FF
RAH2
RAH2
Receive Address Byte Low Register 1 (Read/Write)
Value after reset: FF
RAL1
Data Sheet
7
7
7
Inverse HDLC Operation - HDLC Channel 1
Setting this bit selects the HDLC channel 1 operation mode.
0
1
Value of the First Individual High Address Byte
Bit 1 (C/R-bit) is excluded from address comparison.
Value of Second Individual High Address Byte
H
H
H
Normal operation, HDLC attached to line side
Inverse operation, HDLC attached to system side.
HDLC data is received on XDI and transmitted on RDO.
Transmit time slot configuration is done in RTR(4:1), receive
time slot configurarion is done in TTR(4:1).
360
1
0
Rev. 1.1, 2005-06-13
T1/J1 Registers
PEF 2256 H/E
0
0
0
FALC
(04)
(05)
(06)
®
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