PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 445
PEF2256EV22NP
Manufacturer Part Number
PEF2256EV22NP
Description
Manufacturer
Lantiq
Datasheet
1.PEF2256EV22NP.pdf
(533 pages)
Specifications of PEF2256EV22NP
Number Of Transceivers
1
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Supplier Unconfirmed
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CRC Error Counter (Read)
CECL
CECH
CR(15:0)
Data Sheet
CR15
CR7
7
7
CRC Errors
No function if CRC6 procedure or ESF format are disabled.
In ESF mode, the 16-bit counter is incremented when a multiframe
has been received with a CRC error. CRC errors are not counted
during asynchronous state. The error counter does not roll over.
During alarm simulation, the counter is incremented once per
multiframe.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DCEC is
automatically reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
445
Rev. 1.1, 2005-06-13
T1/J1 Registers
PEF 2256 H/E
CR0
CR8
0
0
FALC
(54)
(55)
®
56
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