PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 242

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Common Configuration Register 2 (Read/Write)
Value after reset: 00
CCR2
Note: Unused bits have to be cleared.
RADD
RCRC
XCRC
Data Sheet
7
Receive Address Pushed to RFIFO - HDLC Channel 1
If this bit is set, the received HDLC address information (1 or 2 bytes,
depending on the address mode selected by MODE.MDS0) is pushed
to RFIFO. This function is applicable in non-auto mode and
transparent mode 1.
RADD must be set, if SS7 mode is selected.
Receive CRC on/off - HDLC Channel 1
Only applicable in non-auto mode.
If this bit is set, the received CRC checksum is written to RFIFO
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed by the status information byte
(contents of register RSIS). The received CRC checksum is
additionally checked for correctness. If non-auto mode is selected,
the limits for “valid frame” check are modified (refer to RSIS.VFR).
Transmit CRC on/off - HDLC Channel 1
If this bit is set, the CRC checksum is not generated internally. It has
to be written to the transmit FIFO as the last two bytes. The
transmitted frame is closed automatically with a closing flag.
Note: The FALC
H
i.e. the number of bytes to be transmitted makes sense or not.
®
RADD
56 does not check whether the length of the frame,
242
RCRC
XCRC
Rev. 1.1, 2005-06-13
PEF 2256 H/E
E1 Registers
0
FALC
(0A)
®
56