PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 22

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2. Fixed pattern with no consecutive 1s might show reduced BPVs in case B8ZS line
Table 2
[ TS24
00010000F00010000
00010000000010000
0001000VB0VBV0000
2.2
In inverse HDLC mode the HDLC data on RDO is inserted only at the last clock cycle of
the data bit. If clock and data rate are equal, data is inserted correctly. If using a clock
rate higher than the data rate the HDLC data can only be sampled at the last clock cycle
of the bit. If there are for example four clock cycles per bit (2.048 Mbit/s and 8.196 MHz
or 1.544 Mbit/s and 6.176 MHz) the HDLC data can only be sampled at the fourth clock
cycle of the corresponding bit.
Therefore either system interface configurations with one clock cycle per bit must be
used or sampling of the data on the receiving system interface device with the last clock
cycle of a bit must be done.
2.3
This restriction is only relevant if HDLC and BOM are used simultaneously on the DL
channel in T1 ESF mode.
Data Sheet
- Alternating 1/0 (50% 1 s density): all BPVs will be detected
- All fixed patterns with no consecutive 1 s (less than 50% 1s density): all BPVs will
be detected.
- Variable or fixed patterns with at least 2 consecutive 1 s will show reduced BPVs.
Reduction of BPVs depends on density of 1s . As 1s density increases, BPV rate
will decrease until the limiting case of all 1s.
- Framed all 1 s: no BPVs will be detected, except a BPV following a framing bit that
is 0.
It is assumed that BPVs are introduced randomly into the data stream. BPVs
adjacent to the framing bit pattern will affect the predicted BPV rate by about
1/400.
coding is used. In this case a BPV directly following a B8ZS substitution pattern will
not be counted. As an example a framed continuos 00010000 pattern can show
reduced BPV count due to B8ZS substitution around F-Bit positions when the F-bit
equals zero and the BPV is inserted at the 1-bit position of TS1. This is also illustrated
in
Table 2
]F[ TS1
Inverse HDLC Mode
Parallel Operation of HDLC and BOM
Code Violations in Framed Fixed Pattern Example
]
[ TS24
000+0000F000-0000
000+00000000-0000
000+000+-0-++0000
]F[ TS1
22
]
description
TS24, F-bit position, TS1
AMI coding with F-Bit = 0
B8ZS coding with BPV
error inserted in TS1
Functional Restrictions
Rev. 1.1, 2005-06-13
PEF 2256 H/E
FALC
®
56