XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 20

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 17: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
3.
Clock-to-Output Times
T
The numbers in this table are tested using the methodology presented in
Table 7
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from
DCM output jitter is included in all measurements.
Symbol
ICKOFDCM
T
ICKOF
and
Table
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
When reading from OFF, the time
from the active transition on the
Global Clock pin to data appearing
at the Output pin. The DCM is not
in use.
10.
Table
Description
22. If the latter is true, add the appropriate Output adjustment from
LVCMOS25
output drive, Fast slew
rate, with DCM
LVCMOS25
output drive, Fast slew
rate, without DCM
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Conditions
(2)
(2)
, 12 mA
, 12 mA
(3)
Table 26
and are based on the operating conditions set forth in
XC3SD1800A
XC3SD3400A
XC3SD1800A
XC3SD3400A
Device
Table
25.
Max
3.28
3.36
5.23
5.51
-5
Speed Grade
Max
3.51
3.82
5.58
6.13
-4
Units
ns
ns
ns
ns
20