XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 77

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

Table 66: Spartan-3A DSP FG676 Pinout for
XC3SD1800A FPGA (Cont’d)
DS610 (v3.0) October 4, 2010
Product Specification
Bank
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VCCO_0
VCCO_0
VCCO_0
IO_L01P_1/HDC
IO_L01N_1/LDC2
IO_L13P_1
IO_L13N_1
IO_L15P_1
IO_L15N_1
IP_L16N_1
IO_L04P_1
IO_L04N_1
IO_L18P_1
IO_L08P_1
IO_L08N_1
IO_L10P_1
IO_L18N_1
IO_L21P_1
IO_L19P_1
IO_L19N_1
IP_L20N_1/VREF_1
IO_L12N_1
IO_L12P_1
IO_L10N_1
IO_L14P_1
IO_L21N_1
IO_L23P_1
IO_L23N_1/VREF_1
IP_L24N_1/VREF_1
IO_L17N_1
IO_L17P_1
IO_L14N_1
IO_L26P_1/A4
IO_L26N_1/A5
IO_L27N_1/A7
IO_L27P_1/A6
IO_L22P_1
IO_L22N_1
IO_L25P_1/A2
XC3SD1800A Pin Name
FG676
W20
W21
W23
Ball
B11
B16
B22
Y20
Y21
Y22
Y23
Y24
Y25
Y26
V18
V19
V21
V22
V23
V24
V25
V26
U18
U19
U20
U21
U22
U23
U24
U26
T17
T18
T20
R17
R18
R19
R20
R21
T23
T24
INPUT
VCCO
VCCO
VCCO
DUAL
DUAL
VREF
VREF
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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Table 66: Spartan-3A DSP FG676 Pinout for
XC3SD1800A FPGA (Cont’d)
Bank
Spartan-3A DSP FPGA Family: Pinout Descriptions
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L31N_1/TRDY1/RHCLK3
IO_L25N_1/A3
IP_L28P_1/VREF_1
IP_L28N_1
IO_L29P_1/A8
IO_L29N_1/A9
IO_L34P_1/IRDY1/RHCLK6
IO_L30N_1/RHCLK1
IO_L30P_1/RHCLK0
IO_L37P_1
IO_L33P_1/RHCLK4
IO_L31P_1/RHCLK2
IO_L39N_1/A15
IO_L39P_1/A14
IO_L34N_1/RHCLK7
IO_L42P_1/A16
IO_L37N_1
IP_L36N_1
IO_L33N_1/RHCLK5
IP_L32N_1
IP_L32P_1
IO_L47N_1
IO_L47P_1
IO_L42N_1/A17
IO_L45P_1
IO_L45N_1
IO_L38N_1/A13
IP_L36P_1/VREF_1
IO_L35N_1/A11
IO_L35P_1/A10
IO_L55N_1
IO_L55P_1
IO_L53P_1
IO_L50P_1
IP_L40N_1
IO_L38P_1/A12
IO_L57N_1
IO_L57P_1
IO_L53N_1
XC3SD1800A Pin Name
FG676
M18
M19
M20
M21
M22
M23
M24
M25
M26
Ball
R22
R23
R24
R25
R26
P18
P20
P21
P22
P23
P25
P26
N17
N18
N19
N20
N21
N23
N24
N25
N26
K18
K19
K20
L17
L18
L20
L22
L23
L24
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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