XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 62

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

DS610 (v3.0) October 4, 2010
Introduction
This section describes how the various pins on a Spartan®-3A DSP FPGA connect within the supported component
packages and provides device-specific thermal characteristics. For general information on the pin functions and the package
characteristics, see the Packaging section in UG331: Spartan-3 Generation FPGA User Guide.
Spartan-3A DSP FPGAs are available in both standard and Pb-free, RoHS versions of each package, with the Pb-free
version adding a “G” to the middle of the package code. Except for the thermal characteristics, all information for the
standard package applies equally to the Pb-free package.
Pin Types
Most pins on a Spartan-3A DSP FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3A DSP packages, as outlined in
the individual pins are color-coded according to pin type as in the table.
Table 57: Types of Pins on Spartan-3A DSP FPGAs
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DS610 (v3.0) October 4, 2010
Product Specification
Type/Color
CONFIG
INPUT
VREF
Code
DUAL
CLK
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form
differential I/Os.
Unrestricted, general-purpose input-only pin. This pin does not have an output structure,
differential termination resistor, or PCI clamp diode.
Dual-purpose pin used in some configuration modes during the configuration process and
then usually available as a user I/O after configuration. If the pin is not used during
configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation
Configuration User Guide for additional information on these signals.
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF
pins in the same bank, provides a reference voltage input for certain I/O standards. If used for
a reference voltage within a bank, all VREF pins within the bank must be connected.
Either a user-I/O pin or an input to a specific clock buffer driver. Packages have 16 global clock
inputs that optionally clock the entire device. The RHCLK inputs optionally clock the right half
of the device. The LHCLK inputs optionally clock the left half of the device. See the Using
Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package
has two dedicated configuration pins. These pins are powered by VCCAUX. See the UG332:
Spartan-3 Generation Configuration User Guide for additional information on the DONE and
PROG_B signals.
101
Description
www.xilinx.com
Spartan-3A DSP FPGA Family:
Table
57. In the package footprint drawings that follow,
Pinout Descriptions
IO_#
IO_Lxxy_#
IP_#
IP_Lxxy_#
M[2:0]
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
IP/VREF_#
IP_Lxxy_#/VREF_#
IO/VREF_#
IO_Lxxy_#/VREF_#
IO_Lxxy_#/GCLK[15:0],
IO_Lxxy_#/LHCLK[7:0],
IO_Lxxy_#/RHCLK[7:0]
DONE, PROG_B
Product Specification
Pin Name(s) in Type
62