XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 57

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

Table 53: Configuration Timing Requirements for Attached SPI Serial Flash
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
T
T
T
T
f
C
CCS
DSU
DH
V
Symbol
or f
These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
Subtract additional printed circuit board routing delay as required by the application.
R
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
T
T
T
CCS
DSU
V
T
f
≤
C
DH
≤
≤
≥
Requirement
T
MCCLn
≤
-------------------------------- -
T
T
T
CCLKn min
MCCL1
MCCL1
T
MCCH1
1
–
(
T
–
–
DCC
T
T
)
CCO
CCO
Units
MHz
ns
ns
ns
ns
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