XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 96

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

User I/Os by Bank
Table 69
AWAKE pin is counted as a dual-purpose I/O.
Table 69: User I/Os Per Bank for the XC3SD3400A in the FG676 Package
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
Top
Right
Bottom
Left
Package
TOTAL
26 VREF are on INPUT pins.
Edge
indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The
I/O Bank
0
1
2
3
Maximum I/Os
Input-Only
and
111
123
112
123
469
314
I/O
82
67
68
97
www.xilinx.com
INPUT
Spartan-3A DSP FPGA Family: Pinout Descriptions
11
34
8
6
9
All Possible I/O Pins by Type
DUAL
30
21
52
1
0
VREF
10
37
9
9
9
(1)
CLK
32
8
8
8
8
96