XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 60

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

IEEE 1149.1/1532 JTAG Test Access Port Timing
X-Ref Target - Figure 15
Table 56: Timing for the JTAG
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
T
T
F
Symbol
TCKTDO
TDITCK
TMSTCK
TCKTDI
TCKTMS
CCH
CCL
CCHDNA
CCLDNA
TCK
The numbers in this table are based on the operating conditions set forth in
For details on JTAG, see Chapter 9, “JTAG Configuraton Mode and Boundary-Scan” in UG332: Spartan-3 Generation Configuration User
Guide.
TCK
TMS
TDI
TDO
(Input)
(Input)
(Input)
(Output)
The time from the falling transition on the TCK pin to data appearing at the TDO pin
The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
(2)
Test Access Port
T
TDITCK
T
TMSTCK
All functions except ISC_DNA command
Figure 15: JTAG Waveforms
All functions except those shown below
Boundary scan commands
(INTEST, EXTEST, SAMPLE)
All functions except those shown below
Configuration commands (CFG_IN, ISC_PROGRAM)
During ISC_DNA command
BYPASS or HIGHZ instructions
All operations except for BYPASS or HIGHZ instructions
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
T
TCKTDI
T
TCKTMS
Table
7.
T
TCKTDO
T
CCH
1/F
TCK
T
CCL
13.0
Min
1.0
7.0
7.0
3.5
10
10
0
0
5
5
0
All Speed
Grades
DS099_06_090610
10,000
10,000
Max
11.0
33
20
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
60