XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 26

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

Input Timing Adjustments
Table 22: Input Timing Adjustments by IOSTANDARD
DS610 (v3.0) October 4, 2010
Product Specification
Single-Ended Standards
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
Following Signal Standard
Convert Input Time from
LVCMOS25 to the
(IOSTANDARD)
Adjustment Below
0.62
0.54
0.00
0.83
0.60
0.31
0.41
0.41
0.72
0.77
0.69
0.69
0.79
0.71
0.71
0.68
0.68
0.78
0.78
Speed Grade
-5
Add the
0.69
0.71
0.68
0.78
0.62
0.54
0.00
0.83
0.60
0.31
0.41
0.41
0.72
0.77
0.69
0.79
0.71
0.68
0.78
-4
Units
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Table 22: Input Timing Adjustments by IOSTANDARD
Notes:
1.
2.
Differential Standards
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Following Signal Standard
Convert Input Time from
The numbers in this table are tested using the methodology
presented in
set forth in
These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
LVCMOS25 to the
(IOSTANDARD)
Table
Table 26
7,
Table
and are based on the operating conditions
10, and
Adjustment Below
0.76
0.79
0.79
0.78
0.79
0.78
0.79
0.79
0.77
0.79
0.79
0.79
0.74
0.72
1.05
0.72
1.05
0.71
0.71
0.74
0.75
1.06
1.06
Speed Grade
-5
Table
Add the
12.
0.76
0.79
0.79
0.78
0.79
0.78
0.79
0.79
0.77
0.79
0.79
0.79
0.74
0.72
1.05
0.72
1.05
0.71
0.71
0.74
0.75
1.06
1.06
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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