XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 98

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

DS610 (v3.0) October 4, 2010
Product Specification
VCCINT
VCCINT
VCCINT VCCINT
VCCINT
VCCO_2
VCCAUX
VREF_0
L31P_2
L27P_2
GCLK0
L27N_2
GCLK1
L29N_2
L29P_2
L28N_2
GCLK3
L28P_2
GCLK2
L26N_0
INPUT
L24N_0
INPUT
L25N_0
GCLK7
L26P_0
GCLK6
L24P_0
GCLK5
L25P_0
GCLK4
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
14
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT
VCCINT
VCCINT
AWAKE
INPUT
VREF_2
L35P_2
L31N_2
L34N_2
L34P_2
L30N_2
L30P_2
L32P_2
L32N_2
VREF_0
INPUT
INIT_B
L23N_0
L23P_0
L22N_0
L20N_0
L20P_0
L16P_0
L16N_0
L35N_2
CSI_B
DOUT
MOSI
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D3
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
VCCO_2
VCCO_2
VCCINT
VCCINT
VCCINT
VREF_2
VCCO_0
VCCAUX
VCCO_0
L42P_2
INPUT
L38N_2
L38P_2
INPUT
L21N_0
L22P_0
L12P_0
L12N_0
L42N_2
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
16
I/O
I/O
I/O
I/O
I/O
∇
VCCAUX
VCCINT
VREF_2
VCCAUX
INPUT
INPUT
VREF_0
L46N_2
L46P_2
L43N_2
L43P_2
L33N_2
L33P_2
INPUT
INPUT
Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top View–Right Half)
L19N_0
L19P_0
L21P_0
L13N_0
L13P_0
L08N_0
L08P_0
L55N_1
L39N_1
L27N_1
L17N_1
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
A15
∇
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A7
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
RHCLK6
L08P_1
L47N_2
L47P_2
L36N_2
L36P_2
INPUT
INPUT
L18N_0
L18P_0
L17N_0
L17P_0
L57N_1
L55P_1
L47N_1
L39P_1
L34P_1
L27P_1
L17P_1
L12N_1
GND
GND
IRDY1
I/O
I/O
I/O
I/O
I/O
A14
∇
∇
∇
D1
D2
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
A6
Bank 0
VCCINT
VCCO_2
VCCO_0
VCCO_1
VCCO_1
L08N_1
L40N_2
L37N_2
VREF_0
RHCLK7
L40P_2
L37P_2
L15N_0
L15P_0
L02N_0
L02P_0
L59P_1
L57P_1
L47P_1
L34N_1
L22P_1
L12P_1
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
∇
∇
19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
Bank 2
SUSPEN
VCCAUX
INPUT
VREF_2
VREF_0
RHCLK1
L04P_1
L01P_1
L41N_2
L41P_2
L39N_2
L39P_2
L14N_0
L14P_0
L11N_0
L11P_0
L01N_0
L01P_0
L64P_1
L59N_1
L53N_1
L53P_1
L42N_1
L42P_1
L30N_1
L22N_1
L14N_1
L10N_1
GND
HDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A24
A17
A16
I/O
∇
20
I/O
I/O
I/O
∇
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D
RHCLK0
L10P_1
L04N_1
L01N_1
DONE
L45N_2
L44N_2
L44P_2
L09N_0
L09P_0
L10N_0
L10P_0
L64N_1
L62N_1
L62P_1
L50N_1
L45P_1
L37N_1
L30P_1
L25P_1
L14P_1
GND
GND
LDC2
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
A25
A21
A20
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2
VCCAUX
VCCO_1
VCCO_2
VREF_2
VCCO_0
VCCAUX
VCCO_1
VCCO_1
VCCAUX
L18N_1
INPUT
VREF_1
L13P_1
L09P_1
L45P_2
L07N_0
L05N_0
L58N_1
L49N_1
L46N_1
L45N_1
L25N_1
L21N_1
L05P_0
L58P_1
L50P_1
L37P_1
I/O
I/O
I/O
I/O
I/O
22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A3
2
VCCAUX
RHCLK4
VREF_1
L21P_1
L18P_1
L13N_1
L09N_1
L07P_1
L03P_1
L48N_2
L48P_2
INPUT
INPUT
INPUT
L07P_0
L06N_0
L06P_0
L56N_1
L51P_1
L49P_1
L46P_1
L40N_1
L38N_1
L36N_1
L33P_1
L28P_1
L26P_1
L23P_1
GND
GND
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A13
I/O
A0
∇
23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
A4
DIN/MISO
VCCAUX
VREF_1
RHCLK5
L19P_1
L15P_1
L11P_1
L07N_1
L03N_1
L52N_2
L52P_2
VREF_1
VREF_1
L61N_1
L56P_1
L54N_1
L51N_1
INPUT
INPUT
L40P_1
L38P_1
INPUT
L36P_1
L33N_1
INPUT
L28N_1
L26N_1
L23N_1
GND
GND
CCLK
www.xilinx.com
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A12
A1
D0
24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
A5
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VREF_1
RHCLK3
L19N_1
L15N_1
L11N_1
L05N_1
L02N_1
L51N_2
L51P_2
L63N_1
INPUT
L43N_1
L35N_1
INPUT
L32N_1
L31N_1
L61P_1
L54P_1
L41P_1
TRDY1
L29P_1
GND
LDC0
GND
GND
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
25
I/O
A23
I/O
I/O
I/O
A19
I/O
I/O
A11
I/O
I/O
∇
∇
∇
∇
∇
A8
VCCAUX
VCCAUX
INPUT
VREF_1
INPUT
VREF_1
VREF_1
RHCLK2
VREF_1
L06N_1
L06P_1
L05P_1
L02P_1
INPUT
INPUT
INPUT
INPUT
L63P_1
L60N_1
L60P_1
L43P_1
L41N_1
L35P_1
L32P_1
L31P_1
L29N_1
GND
LDC1
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
A22
A18
A10
∇
∇
∇
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
A9
∇
Spartan-3A DSP FPGA Family: Pinout Descriptions
W
V
Y
A
A
A
B
A
C
A
D
A
E
A
M
F
A
B
C
D
E
F
G
H
K
L
N
P
R
T
U
J
Right Half of FG676
Package (Top View)
98