XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 54

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

Master Serial and Slave Serial Mode Timing
X-Ref Target - Figure 11
Table 50: Timing for the Master Serial and Slave Serial Configuration Modes
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
(Input/Output)
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
(Open-Drain)
CCO
DCC
CCD
CCH
CCL
CCSER
Symbol
PROG_B
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
(Output)
INIT_B
(Input)
(Input)
CCLK
DOUT
DIN
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at the
CCLK input pin
Figure 11: Waveforms for Master Serial and Slave Serial Configuration
(2)
Description
T
DCC
Bit 0
No bitstream compression
With bitstream compression
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
T
CCD
Bit 1
Table
7.
T
T
Master
Master
Master
Master
Slave/
MCCL
SCCL
Slave
Slave
Slave
Slave
Both
Both
Bit n
1/F
CCSER
T
CCO
Bit n-64
Bit n+1
All Speed Grades
Min
1.5
0.0
1.0
T
7
0
0
T
SCCH
MCCH
See
See
See
See
Bit n-63
Table 48
Table 49
Table 48
Table 49
Max
100
100
10
–
–
–
DS312-3_05_103105
Units
MHz
MHz
ns
ns
ns
ns
54