LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet - Page 10

• Manufacturer Part Number: LH7A400N0F000B5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B5

• Lead Free Status / RoHS Status: Compliant

LH7A400
10
BGA
PIN
M6
M7
M8
N6
N4
P4
R4
N7
P8
P5
R5
R6
R8
L6
T4
T5
LFBGA
PIN
M7
R3
R4
R6
R7
R9
P4
T2
P5
T3
P6
T4
T5
P7
T6
T7
PG2/
nPCIOR
PG3/
nPCIOW
PG4/nPCREG
PG5/nPCCE1
PG6/nPCCE2
PG7/PCDIR
PH0/
PCRESET1
PH1/CFA8/
PCRESET2
PH2/
nPCSLOTE1
PH3/CFA9/
PCMCIAA25/
nPCSLOTE2
PH4/
nPCWAIT1
PH5/CFA10/
PCMCIAA24/
nPCWAIT2
PH6/
nAC97RESET
PH7/
nPCSTATRE
LCDFP
LCDLP
SIGNAL
• GPIO Port G
• I/O Read Strobe for PC Card (PCMCIA or CF) in
• GPIO Port G
• I/O Write Strobe for PC Card (PCMCIA or CF) in
• GPIO Port G
• Register Memory Access for PC Card (PCMCIA
• GPIO Port G
• Card Enable 1 for PC Card (PCMCIA or CF) in
• GPIO Port G
• Card Enable 2 for PC Card (PCMCIA or CF) in
• GPIO Port G
• Direction for PC Card (PCMCIA or CF) in single
• GPIO Port H
• Reset Card 1 for PC Card (PCMCIA or CF) in sin-
• GPIO Port H
• Address Bit 8 for PC Card (CF) in single card mode
• Reset Card 2 for PC Card (PCMCIA or CF) in
• GPIO Port H
• Enable Card 1 for PC Card (PCMCIA or CF) in sin-
• GPIO Port H
• Address Bit 9 for PC Card (CF) in single card mode
• Address Bit 25 for PC Card (PCMCIA) in single
• Enable Card 2 for PC Card (PCMCIA or CF) in
• GPIO Port H
• WAIT Signal for Card 1 for PC Card (PCMCIA or
• GPIO Port H
• Address Bit 10 for PC Card (CF) in single
• Address Bit 24 for PC Card (PCMCIA) in single
• WAIT Signal for Card 2 for PC Card (PCMCIA or
• GPIO Port H
• Audio Codec (AC97) Reset
• GPIO Port H
• Status Read Enable for PC Card (PCMCIA or F)
LCD Frame Synchronization pulse
LCD Line Synchronization pulse
single or dual card mode
single or dual card mode
or CF) in single or dual card mode
single or dual card mode. This signal and
nPCCE2 are used by the PC Card for decoding
low and high byte accesses.
single or dual card mode. This signal and
nPCCE1 are used by the PC Card for decoding
low and high byte accesses.
or dual card mode
gle or dual card mode
dual card mode
gle or dual card mode. This signal is used for gating
other control signals to the appropriate PC Card.
card mode
dual card mode. This signal is used for gating
other control signals to the appropriate PC Card.
CF) in single or dual card mode
card mode
card mode
F) in dual card mode
in single or dual card mode
Table 3. Functional Pin List (Cont’d)
DESCRIPTION
Rev. 01 — 16 July 2007
NXP Semiconductors
LOW: PG2
LOW: PG3
LOW: PG4
LOW: PG5
LOW: PG6
LOW: PG7
Input: PH0
Input: PH1
Input: PH2
Input: PH3
Input: PH4
Input: PH5
Input: PH6
Input: PH7
RESET
STATE
LOW
LOW
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
STANDBY
STATE
LOW
LOW
32-Bit System-on-Chip
Preliminary data sheet
OUTPUT
DRIVE
12 mA
12 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
I/O NOTES
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O