LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet - Page 28

• Manufacturer Part Number: LH7A400N0F000B5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B5

• Lead Free Status / RoHS Status: Compliant

LH7A400
Real Time Clock (RTC)
tion or long time-base counter. This is achieved by gen-
erating an interrupt signal after counting for a
programmed number of cycles of a real-time clock
input. Counting in one second intervals is achieved by
use of a 1 Hz clock input to the RTC.
Battery Monitor Interface (BMI)
face specified for two types of Battery Monitors/Gas
Gauges. The first type employs a single wire interface.
The second interface employs a two-wire multi-master
bus, the Smart Battery System Specification. If both
interfaces are enabled at the same time, the Single
Wire Interface will have priority. A brief overview of
these two interface types are given here.
SINGLE WIRE INTERFACE
• Serial-to-parallel conversion on data received from
• Parallel-to-serial conversion on data transmitted to
• Data packet coding/decoding on data transfers
protocol, in which the host initiates a data transfer by
sending a WriteData/Command word to the Battery
Monitor. This word will always contain the Command
section, which tells the Single Wire Interface device the
location for the current transaction. The most signifi-
cant bit of the Command determines if the transaction
is Read or Write. In the case of a Write transaction,
then the word will also contain a WriteData section with
the data to be written to the peripheral.
SMART BATTERY INTERFACE
• Serial-to-Parallel conversion on data received from
• Parallel-to-Serial conversion of data transmitted to
master bus (the SMBus), meaning that more than one
device capable of controlling the bus can be connected
to it. A master device initiates a bus transfer and provides
the clock signals. A slave device can receive data pro-
vided by the master or it can provide data to the master.
Since more than one device may attempt to take control
of the bus as a master, SMBus provides an arbitration
mechanism, by relying on the wired-AND connection of
all SMBus interfaces to the SMBus.
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the peripheral device
the peripheral device
(incorporating Start/Data/Stop data packets)
the peripheral device
the peripheral device.
The RTC can be used to provide a basic alarm func-
The LH7A400 BMI is a serial communication inter-
The Single Wire Interface performs:
The Single Wire interface uses a command-based
The SMBus Interface performs:
The Smart Battery Interface uses a two-wire multi-
Rev. 01 — 16 July 2007
NXP Semiconductors
DC-to-DC Converter
• Dual drive PWM outputs, with independent closed
• Software programmable configuration of one of 8
• Software programmable configuration of duty cycle
• Output polarity (for positive or negative voltage gen-
• Each PWM output can be dynamically switched to
Watchdog Timer (WDT)
against malfunctions. It is a programmable timer that is
reset by software at regular intervals. Failure to reset
the timer will cause a FIQ interrupt. Failure to service
the FIQ interrupt will then generate a System Reset.
The WDT features are:
• Driven by the system clock
• 16 programmable time-out periods: 2
• Generates a system reset (resets LH7A400) or a
• Software enable, lockout, and counter-reset mecha-
• Protection mechanism guards against
General Purpose I/O (GPIO)
data register and a data direction register. It also has
added registers including Keyboard Scan, PINMUX,
GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI, and
PGHCON.
port is configured as an input or an output while the
data register is used to read the value of the GPIO pins.
OFEOI registers are used to control edge-triggered
Interrupts on Port F. The PINMUX register controls
what signals are output of Port D and Port E when they
are set as outputs, while the PGHCON controls the
operations of Port G and H.
loop feedback
output frequencies (each being a fixed divide of the
input clock).
from 0 to 15/16, in intervals of 1/16.
eration) is hardware-configured during power-on
reset via the polarity select inputs
one of a pair of preprogrammed frequency/duty
cycle combinations via external pins.
clock cycles
FIQ Interrupt whenever a time-out period is reached
nisms add security against inadvertent writes
interrupt-service-failure:
The features of the DC-DC Converter interface are:
The Watchdog Timer provides hardware protection
– The first WDT time-out triggers FIQ and asserts
– If FIQ service routine fails to clear nWDFIQ, then
The LH7A400 GPIO has eight ports, each with a
The data direction register determines whether a
The GPIO Interrupt Enable, INTYPE1/2, and GPI-
nWDFIQ status flag
the next WDT time-out triggers a System Reset.
32-Bit System-on-Chip
Preliminary data sheet
16
through 2
31