LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet - Page 9

• Manufacturer Part Number: LH7A400N0F000B5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B5

• Lead Free Status / RoHS Status: Compliant

32-Bit System-on-Chip
Preliminary data sheet
BGA
M11
N11
R10
N10
M10
P10
PIN
L11
L10
M9
R2
K8
R9
A6
B6
C6
H8
B5
D6
E6
C5
R3
T1
T2
T9
T3
LFBGA
K10
P10
T11
T12
R11
R12
T13
T10
R10
PIN
M9
N4
R2
N5
C5
D6
M6
T9
K9
A5
B4
E7
B3
A4
A3
T1
PC5/
LCDCLS
PC6/LCDHR-
LP
PC7/
LCDSPL
PD0/LCDVD8
PD1/LCDVD9
PD2/LCDVD10
PD3/LCDVD11
PD4/LCDVD12
PD5/LCDVD13
PD6/LCDVD14
PD7/LCDVD15
PE0/LCDVD4
PE1/LCDVD5
PE2/LCDVD6
PE3/LCDVD7
PF0/INT0
PF1/INT1
PF2/INT2
PF3/INT3
PF4/INT4/
SCVCCEN
PF5/INT5/
SCDETECT
PF6/INT6/
PCRDY1
PF7/INT7/
PCRDY2
PG0/nPCOE
PG1/nPCWE
SIGNAL
• GPIO Port C
• HR-TFT Row Driver Clock
• GPIO Port C
• LCD Latch Pulse
• GPIO Port C
• LCD Start Pulse Left
• GPIO Port D
• LCD Video Data Bus
• GPIO Port E
• LCD Video Data Bus
• GPIO Port F
• External FIQ Interrupt. Interrupts can be level or
• GPIO Port F
• External IRQ Interrupts. Interrupts can be level or
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
• Smart Card Supply Voltage Enable
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
• Smart Card Detection
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
• Ready for Card 1 for PC Card (PCMCIA or CF) in
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
• Ready for Card 2 for PC Card (PCMCIA or CF) in
• GPIO Port G
• Output Enable for PC Card (PCMCIA or CF) in
• GPIO Port G
• Write Enable for PC Card (PCMCIA or CF) in sin-
edge triggered and are internally debounced.
edge triggered and are internally debounced.
edge triggered and are internally debounced.
edge triggered and are internally debounced.
edge triggered and are internally debounced.
edge triggered and are internally debounced.
single or dual card mode
edge triggered and are internally debounced.
single or dual card mode
single or dual card mode
gle or dual card mode
Table 3. Functional Pin List (Cont’d)
DESCRIPTION
Rev. 01 — 16 July 2007
NXP Semiconductors
LOW: PC5
LOW: PC6
LOW: PC7
LOW: PD0
LOW: PD1
LOW: PD2
LOW: PD3
LOW: PD4
LOW: PD5
LOW: PD6
LOW: PD7
LOW: PG0
LOW: PG1
Input: PE0
Input: PE1
Input: PE2
Input: PE3
Input: PF0
Input: PF1
Input: PF2
Input: PF3
Input: PF4
Input: PF5
Input: PF6
Input: PF7
RESET
STATE
PDOCON = 1
PEOCON = 1
LOW if SCI is
PDOCON or
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
STANDBY
(bits [1:0]);
otherwise,
PINMUX:
PINMUX:
otherwise
otherwise
Enabled;
STATE
LOW if
LOW if
(bit 1);
OUTPUT
DRIVE
12 mA
12 mA
12 mA
12 mA
12 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
I/O NOTES
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LH7A400
3
3
3
3
3
3
3
3
9