LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet - Page 22

• Manufacturer Part Number: LH7A400N0F000B5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B5

• Lead Free Status / RoHS Status: Compliant

LH7A400
AMBA APB BUS
peripheral data bus. The speed of this bus is selectable
to be a divide-by-2, divide-by-4 or divide-by-8 of the
speed of the AHB bus.
EXTERNAL BUS INTERFACE
wide, high speed gateway to external memory devices.
The memory devices supported include:
• Asynchronous RAM/ROM/Flash
• Synchronous DRAM/Flash
• PCMCIA interfaces
• CompactFlash interfaces.
nous memory controller or Synchronous memory con-
troller. There is an arbiter on the EBI input, with priority
given to the Synchronous Memory Controller interface.
LCD AHB BUS
that connects it to the system’s embedded memory and
external SDRAM. The function of this local data bus is
to allow the LCD controller to perform its video refresh
function without congesting the AHB bus. This leads to
better system performance and lower power consump-
tion. There is an arbiter on both the embedded memory
and the synchronous memory controller. In both cases
the LCD bus is given priority.
DMA BUSES
higher speed/higher data volume APB peripherals
(MMC, USB and AC97) to the AHB bus. This enables
the efficient transfer of data between these peripherals
and external memory without the intervention of the
ARM922T core. The DMA engine does not support
memory to memory transfers.
Memory Map
This allows it to address up to 4GB of memory. This
memory space is subdivided into a number of memory
banks; see Figure 6. Four of these banks (each of
256MB) are allocated to the Synchronous memory con-
troller. Eight of the banks (again, each 256MB) are allo-
cated to the Asynchronous memory controller. Two of
these eight banks are designed for PCMCIA systems.
Part of the remaining memory space is allocated to the
embedded SRAM, and to the control registers of the
AHB and APB. The rest is unused.
22
The AMBA APB bus is a lower-speed 32-bit-wide
The External Bus Interface (EBI) provides a 32-bit
The EBI can be controlled by either the Asynchro-
The LCD controller has its own local memory bus
The LH7A400 has a DMA system that connects the
The LH7A400 system has a 32-bit-wide address bus.
Rev. 01 — 16 July 2007
NXP Semiconductors
asynchronous ROM/Flash. The selection is determined
by the value of the MEDCHG pin at Power On Reset as
shown in Table 8. When booting from synchronous
memory, then synchronous bank 4 (nSCS3) is mapped
into memory location zero. When booting from asyn-
chronous memory, asynchronous memory bank 0
(nSCS0) is mapped into memory location zero.
system for the two boot modes.
configure the ARM922T MMU to remap the low mem-
ory space to a location in RAM. This allows the user to
set the interrupt vector table.
Interrupt Controller
trol the interrupts from 28 different sources. Four inter-
rupt sources are mapped to the FIQ input of the
ARM922T and 24 are mapped to the IRQ input. FIQs
have a higher priority than the IRQs. If two interrupts
with the same priority become active at the same time,
the priority must be resolved in software.
troller generates an FIQ or IRQ if the corresponding
mask bit is set. No latching of interrupts takes place in
the controller. After a Power On Reset all mask register
bits are cleared, therefore masking all interrupts.
Hence, enabling of the mask register must be done by
software after a power-on-reset.
8-bit ROM
16-bit ROM
32-bit ROM
32-bit ROM
16-bit SFlash
(Initializes Mode Register)
16-bit SROM
(Initializes Mode Register)
32-bit SFlash
(Initializes Mode Register)
32-bit SROM
(Initializes Mode Register)
The LH7A400 can boot from either synchronous or
Figure 6 shows the memory map of the LH7A400
Once the LH7A400 has booted, the boot code can
The LH7A400 interrupt controller is designed to con-
When an interrupt becomes active, the interrupt con-
BOOT MODE
Table 8. Boot Modes
LATCHED
WIDTH1
BOOT-
0
0
1
1
0
0
1
1
32-Bit System-on-Chip
Preliminary data sheet
LATCHED
WIDTH0
BOOT-
0
1
0
1
0
1
0
1
LATCHED
MEDCHG
0
0
0
0
1
1
1
1