LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet - Page 58

• Manufacturer Part Number: LH7A400N0F000B5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B5

• Lead Free Status / RoHS Status: Compliant

LH7A400
Operating Temperature and Noise Immunity
perature of the transistors in the integrated circuit. The
switching speed of the CMOS circuitry within the SoC
depends partly on Tj, and the lower the operating tem-
perature, the faster the CMOS circuits will switch.
Increased switching noise generated by faster switch-
ing circuits could affect the overall system stability. The
amount of switching noise is directly affected by the
application executed on the SoC.
to meet industrial temperature standards should use an
external oscillator rather than a crystal to drive the sys-
tem clock input of the System-on-Chip. This change
from crystal to oscillator will increase the robustness
(i.e., noise immunity of the clock input to the SoC).
Printed Circuit Board Layout Practices
LH7A400 POWER SUPPLY DECOUPLING
for different internal circuitry sections. The VDD and
VSS pins supply power to I/O buffers, while VDDC and
VSSC supply power to the core logic, and VDDA/VSSA
supply analog power to the PLLs.
with a low impedance path to the corresponding board
power supply. Likewise, the VSS, VSSA, and VSSC
pins must be provided with a low impedance path to the
board ground.
using at least one 0.1 µF high frequency capacitor
located as close as possible to a VDDx, VSSx pin pair
on each of the four sides of the chip. If room on the cir-
cuit board allows, add one 0.01 µF high frequency
capacitor near each VDDx, VSSx pair on the chip.
circuit board traces connecting to the chip VDDx, VSSx
pins must be kept to less than half an inch (12.7 mm)
per capacitor lead. There must be one bulk 10 µF
capacitor for each power supply placed near one side
of the chip.
RECOMMENDED PLL, VDDA, VSSA FILTER
cuitry. VSSA is the ground return path for the PLL cir-
cuit. NXP recommends a low-pass filter attached as
shown in Figure 47. The values of the inductor and
capacitors are not critical. The low-pass filter prevents
high frequency noise from adversely affecting the PLL
circuits. The distance from the IC pin to the high fre-
quency capacitor should be as short as possible.
58
The junction temperature, Tj, is the operating tem-
NXP recommends that users implementing a system
The LH7A400 has separate power and ground pins
Each of the VDD and VDDC pins must be provided
Each power supply must be decoupled to ground
To be effective, the capacitor leads and associated
The VDDA pins supply power to the chip PLL cir-
Rev. 01 — 16 July 2007
NXP Semiconductors
UNUSED INPUT SIGNAL CONDITIONING
consumption. Unused inputs without internal pull-up or
pull-down resistors should be pulled up or down exter-
nally (NXP recommends tying HIGH), to tie the signal
to its inactive state. 33 KΩ or less is recommended.
carry these signals are unused, software can program
these signals as outputs, eliminating the need for pull-
ups or pull-downs. Power consumption may be higher
than expected until software completes programming
the GPIO. Some LH7A400 inputs have internal pull-
ups or pull-downs. If unused, these inputs do not
require external conditioning.
OTHER CIRCUIT BOARD LAYOUT PRACTICES
cuit trace interconnection length must therefore be
reduced to minimize overshoot, undershoot and reflec-
tions caused by transmission line effects of these fast
output switching times. This recommendation particu-
larly applies to the address and data buses.
consider all device loads and capacitances due to the
circuit board traces. Capacitance due to the traces will
depend upon a number of factors, including the trace
width, dielectric material the circuit board is made from
and proximity to ground and power planes.
cuit board layout becomes more critical in systems with
higher capacitive loads. As these capacitive loads
increase, transient currents in the power supply and
ground return paths also increase.
(SOURCE)
Floating input signals can cause excessive power
Some GPIO signals default to inputs. If the pins that
All outputs have fast rise and fall times. Printed cir-
When considering capacitance, calculations must
Attention to power supply decoupling and printed cir-
VDDC
Figure 47. VDDA, VSSA Filter Circuit
10 µH
22 µF
+
32-Bit System-on-Chip
Preliminary data sheet
0.1 µF
VSSA
VDDC
VDDA
LH7A400
LH7A400-189