LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet - Page 11

• Manufacturer Part Number: LH7A400N0F000B5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B5

• Lead Free Status / RoHS Status: Compliant

32-Bit System-on-Chip
Preliminary data sheet
BGA
T15
T16
PIN
P9
N9
P7
R7
N8
E7
D7
C7
B7
C4
D5
B4
A4
A3
B3
A2
E2
E3
E5
H4
T7
F2
F3
F4
J7
J1
J2
J3
LFBGA
T16
R16
PIN
M8
N9
R8
C7
C3
D4
G4
G5
G6
G3
P9
P8
T8
A6
B6
B5
A2
A1
B2
E6
B1
E1
F3
F1
J3
J6
J7
J2
LCDENAB/
LCDM
LCDDCLK
LCDVD0
LCDVD1
LCDVD2
LCDVD3
USBDP
USBDN
nPWME0
nPWME1
PWM0
PWM1
ACBITCLK
ACOUT
ACSYNC
ACIN
MMCCLK/
MMSPICLK
MMCCMD/
MMSPIDIN
MMCDATA/
MMSPIDOUT
UARTCTS2
UARTDCD2
UARTDSR2
UARTIRTX1
UARTIRRX1
UARTTX2
UARTRX2
SSPCLK
SSPRX
SSPTX
SSPFRM/
nSSPFRM
SIGNAL
LCD TFT Data Enable
LCD STN AC Bias
LCD Data Clock
LCD Video Data Bus
USB Data Positive (Differential Pair)
USB Data Negative (Differential Pair)
• DC-DC Converter Pulse Width
• Modulator 0 Enable
• DC-DC Converter Pulse Width
• Modulator 1 Enable
• DC-DC Converter Pulse Width
• Modulator 0 Output during normal operation and
• DC-DC Converter Pulse Width
• Modulator 1 Output during normal operation and
• Audio Codec (AC97) Clock
• Audio Codec (ACI) Clock
• Audio Codec (AC97) Output
• Audio Codec (ACI) Output
• Audio Codec (AC97)
• Audio Codec (ACI) Synchronization
• Audio Codec (AC97) Input
• Audio Codec (ACI) Input
• MultiMediaCard Clock (20 MHz MAX.)
• MultiMediaCard SPI Mode Clock
• MultiMediaCard Command
• MultiMediaCard SPI Mode Data Input
• MultiMediaCard Data
• MultiMediaCard SPI Mode Data Output
• UART2 Clear to Send Signal. This pin is an
• UART2 Data Carrier Detect Signal. This pin is
UART2 Data Set Ready Signal
IrDA Transmit
IrDA Receive. This pin is an output for JTAG
boundary scan only.
UART2 Transmit Data Output
UART2 Receive Data Input. This pin is an output
for JTAG boundary scan only.
Synchronous Serial Port Clock
Synchronous Serial Port Receive
Synchronous Serial Port Transmit
Synchronous Serial Port Frame Sync
Polarity Selection input at reset
Polarity Selection input at reset
Synchronization
output for JTAG boundary scan only.
output for JTAG boundary scan only.
Table 3. Functional Pin List (Cont’d)
DESCRIPTION
Rev. 01 — 16 July 2007
NXP Semiconductors
MMCDATA
LCDENAB
MMCCMD
MMCCLK
RESET
STATE
LOW:
LOW:
Input:
Input:
HIGH
LOW
LOW
Input
Input
Input
Input
Input
Input
Input
LOW
LOW
Input
Input
Input
Input
LOW
Input
Input
LOW
Input
LOW
Input
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
STANDBY
STATE
LOW
LOW
LOW
LOW
Input
Input
LOW
Input
OUTPUT
DRIVE
12 mA
12 mA
12 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
I/O NOTES
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
LH7A400
I
I
I
I
I
I
I
I
10
10
11