LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet - Page 27

• Manufacturer Part Number: LH7A400N0F000B5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B5

• Lead Free Status / RoHS Status: Compliant

32-Bit System-on-Chip
Audio Codec Interface (ACI)
• A digital serial interface to an off-chip 8-bit CODEC
• All the necessary clocks and timing pulses to per-
transmit and receive paths are buffered with internal
FIFO memories allowing up to 16 bytes to be stored
independently in both transmit and receive modes.
that generates a common transmit and receive bit clock
output from the on-chip ACI clock input (ACICLK).
Transmit data values are output synchronous with the
rising edge of the bit clock output. Receive data values
are sampled on the falling edge of the bit clock output.
The start of a data frame is indicated by a synchroniza-
tion output signal that is synchronous with the bit clock.
Synchronous Serial Port (SSP)
synchronous serial communication with device periph-
eral devices that has either Motorola SPI, National
Semiconductor MICROWIRE or Texas Instruments
Synchronous Serial Interfaces.
version on data received from a peripheral device. The
transmit and receive paths are buffered with internal
FIFO memories allowing up to eight 16-bit values to be
stored independently in both transmit and receive
modes. Serial data is transmitted on SSPTXD and
received on SSPRXD.
clock divider and prescaler to generate the serial output
clock SCLK from the input clock SSPCLK. Bit rates are
supported to 2 MHz and beyond, subject to choice of
frequency for SSPCLK; the maximum bit rate will usu-
ally be determined by peripheral devices.
UART/IrDA
UART2, and UART3.
• Serial-to-Parallel conversion on data received from
• Parallel-to-Serial conversion on data transmitted to
Preliminary data sheet
form serialization or de-serialization of the data
stream to or from the CODEC device.
the peripheral device
the peripheral device.
The ACI provides:
The interface supports full duplex operation and the
The ACI includes a programmable frequency divider
The LH7A400 SSP is a master-only interface for
The LH7A400 SSP performs serial-to-parallel con-
The LH7A400 SSP includes a programmable bit rate
The LH7A400 contains three UARTs, UART1,
The UART performs:
Rev. 01 — 16 July 2007
NXP Semiconductors
nal FIFO memories allowing up to 16 bytes to be stored
independently in both transmit and receive modes.
• Four individually maskable interrupts from the
• A single combined interrupt so that the output is
reception, the appropriate error bit is set, and is stored
in the FIFO. If an overrun condition occurs, the overrun
register bit is set immediately and the FIFO data is pre-
vented from being overwritten. UART1 also supports
IrDA 1.0 (15.2 kbit/s).
(CTS), Data Carrier Detect (DCD) and Data Set Ready
(DSR) are supported on UART2 and UART3.
Timers
Each of these timers has an associated 16-bit read/write
data register and a control register. Each timer is loaded
with the value written to the data register immediately,
this value will then be decremented on the next active
clock edge to arrive after the write. When the timer
underflows, it will immediately assert its appropriate
interrupt. The timers can be read at any time. The clock
source and mode is selectable by writing to various bits
in the system control register. Clock sources are
508 kHz and 2 kHz.
clocked from a single 7.3728 MHz source. It has the
same register arrangement as Timer 1 and Timer 2, pro-
viding a load, value, control and clear register. Once the
timer has been enabled and is written to, unlike the
Timer 1 and Timer 2, will decrement the timer on the
next rising edge of the 7.3728 MHz clock after the data
register has been updated. All the timers can operate in
two modes, free running mode or pre-scale mode.
FREE-RUNNING MODE
0xFFFF when it underflows and continue counting down.
PRE-SCALE MODE
each timer is automatically re-loaded when the timer
underflows. This mode can be used to produce a pro-
grammable frequency to drive an external buzzer or
generate a periodic interrupt.
receive, transmit and modem status logic blocks
asserted if any of the individual interrupts are
asserted and unmasked.
The transmit and receive paths are buffered with inter-
The UART can generate:
If a framing, parity, or break error occurs during
The modem status input signals Clear to Send
Two identical timers are integrated in the LH7A400.
Timer 3 (TC3) has the same basic operation, but is
In free-running mode, the timer will wrap around to
In pre-scale (periodic) mode, the value written to
LH7A400
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