LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet - Page 25

• Manufacturer Part Number: LH7A400N0F000B5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B5

• Lead Free Status / RoHS Status: Compliant

32-Bit System-on-Chip
functions:
• Memory bank select
• Access sequencing
• Wait states generation
• Byte lane write control
• External bus interface
• CompactFlash or PCMCIA interfacing.
Synchronous Memory Controller
speed memory interface to a wide variety of Synchro-
nous memory devices, including SDRAM, Synchro-
nous Flash and Synchronous ROMs.
• LCD DMA port for high bandwidth
• Up to four Synchronous Memory banks that can be
• Special configuration bits for Synchronous ROM
• Ability to program Synchronous Flash devices using
• On booting from Synchronous ROM, (and optionally
• Data is transferred between the controller and the
• Programmable for 16- or 32-bit data bus size
• Two reset domains are provided to enable SDRAM
• Power saving Synchronous Memory SCKE and
MultiMediaCard (MMC)
and functions of an MMC host. The adapter supports
the full MMC bus protocol, defined by the MMC Defini-
tion Group’s specification v.2.11. The controller can
also implement the SPI interface to the cards.
INTERFACE DESCRIPTION AND MMC OVERVIEW
bus (clock, command, and data) to transfer data to and
from the MMC card, and to configure and acquire status
information from the card’s registers.
Preliminary data sheet
independently set up
operation
write and erase commands
with Synchronous Flash), a configuration sequence is
performed before releasing the processor from reset
SDRAM in quad-word bursts. Longer transfers within
the same page are concatenated, forming a seam-
less burst
contents to be preserved over a ‘soft’ reset
external clock modes provided.
The Asynchronous Memory Controller has six main
The Synchronous memory controller provides a high
The key features of the controller are:
The MMC adapter combines all of the requirements
The MMC controller uses the three-wire serial data
Rev. 01 — 16 July 2007
NXP Semiconductors
• Power supply: VDD and VSS
• Data Transfer: MMCCMD, MMCDATA
• Clock: MMCLK.
MULTIMEDIACARD ADAPTER
Card specific functions, serves as the bus master for the
MultiMediacard Bus and implements the standard inter-
face to the MultiMediaCard Cards (card initialization,
CRC generation and validation, command/response
transactions, etc.).
Smart Card Interface (SCI)
Card reader. The SCI can autonomously control data
transfer to and from the smart card. Transmit and
receive data FIFOs are provided to reduce the required
interaction between the CPU core and the peripheral.
SCI FEATURES
• Supports asynchronous T0 and T1 transmission
• Supports clock rate conversion factor F = 372, with
• Eight-character-deep buffered Tx and Rx paths
• Direct interrupts for Tx and Rx FIFO level monitoring
• Interrupt status register
• Hardware-initiated card deactivation sequence on
• Software-initiated card deactivation sequence on
• Limited support for synchronous Smart Cards via
PROGRAMMABLE PARAMETERS
• Smart Card clock frequency
• Communication baud rate
• Protocol convention
• Card activation/deactivation time
• Check for maximum time for first character of
• Check for maximum duration of ATR character
• Check for maximum time of receipt of first character
• Check for maximum time allowed between characters
• Character guard time
• Block guard time
• Transmit/receive character retry.
protocols
bit rate adjustment factors D = 1, 2, or 4 supported
detection of card removal
transaction complete
registered input/output.
Answer to Reset - ATR reception
stream
of data stream
MMC bus lines can be divided into three groups:
The MultiMediaCard Adapter implements MultiMedia-
The SCI (ISO7816) interfaces to an external Smart
LH7A400
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