ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 154

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.2.4 PWM0 Counter Registers (PW0CH, PW0CL)
Address: 0F0A4H
Access: R/W
Access size: 8-bit
Initial value: 00H
Address: 0F0A5H
Access: R/W
Access size: 8-bit
Initial value: 00H
PW0CL and PW0CH are special function registers (SFRs) that function as 16-bit binary counters.
When data is written to either PW0CL or PW0CH, PW0CL and PW0CH is set to “0000H”. The data that is written is
meaningless.
When data is read from PW0CL, the value of PW0CH is latched. When reading PW0CH and PW0CL, use a word type
instruction or pre-read PW0CL.
The contents of PW0CH and PW0CL during PWM operation cannot be read depending on the combination of the PWM
clock and system clock.
Table 10-1 shows PW0CH and PW0CL read enable/disable for each combination of the PWM clock and system clock.
Initial value
Initial value
External clock
PWM clock
PW0CH
PW0CL
HTBCLK
HTBCLK
LSCLK
LSCLK
P0CK
R/W
R/W
Table 10-1 PW0CH and PW0CL Read Enable/Disable during PWM0 Operation
P0C15
P0C7
R/W
R/W
7
0
7
0
System clock
SYSCLK
HSCLK
HSCLK
HSCLK
LSCLK
LSCLK
LSCLK
P0C14
P0C6
R/W
R/W
6
0
6
0
P0C13
P0C5
Read enabled.
Read enabled. However, to prevent the reading of undefined data
during counting, read consecutively PW0CH or PW0CL twice
until the last data coincides the previous data.
Read disabled.
Read enabled.
Read disabled.
R/W
R/W
5
0
5
0
P0C12
P0C4
10-5
PW0CH and PW0CL read enable/disable
R/W
R/W
4
0
4
0
ML610Q407/ML610Q408/ML610Q409 User's Manual
P0C11
P0C3
R/W
R/W
3
0
3
0
P0C10
P0C2
R/W
R/W
0
0
2
2
P0C1
P0C9
R/W
R/W
1
0
1
0
Chapter 10 PWM
P0C0
P0C8
R/W
R/W
0
0
0
0