ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 313

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22. LCD Driver
22.1 Overview
This LSI includes LCD drivers that display the contents that are set in the display register.
For the ML610Q407/Q408/Q409, the numbers of commons and segments and the maximum number of dots are as shown
in Table 22-1.
The LCD display function consists of four blocks as shown in Figure 22-1:
The display registers are used to store the contents to be displayed as bit patterns.
The bit pattern storage method depends on the specification of the LCD panel to be used (display pattern and assignment
of the COM pin and SEG pin) and the setting of the display allocation circuit.
The display allocation block controls mapping of the display register for the LCD common/segment.
Using the display allocation registers A and B or not using them is selectable. When using them (Set DASN bit of
DSPMOD1 register to “1”), the segment mapping of the display register can be specified in bit units by programming
according to the contents of display allocation registers A and B. Therefore, the display register array can be changed in
flexible and simplify the software process for display (This function is defined as the programmable display allocation
function in the User's Manual). Also, the data specified to the registers A and B can be easily prepared by using Oki
semiconductor LCD allocation Tool.
When the display allocation registers A and B are not used (set the DSPMOD1 register's DASN bit to "0"), the display
content is controlled only with the display registers.
The display control circuit generates LCD drive waveforms according to the characteristics of the LCD.
A bias, a bias voltage multiplying clock, a duty, and a frame frequency suitable for the LCD panel can be selected.
1.
2.
3.
4.
DSPR27
DSPR26
DSPR02
DSPR01
DSPR00
Display registers
Display allocation
Display control
Driver
Table 22-1 Numbers of Commons/Segments and Maximum Number of Dots for ML610Q407/8/9
Display registers
commons/segments
Maximum number
(changeable by
Product name
Number of
(ML610...)
software)
of dots
Display allocation
Figure 22-1 Configuration of LCD Display Function
Select by DASN bit (DSPMOD1 register)
Allocation
Allocation
Registers
A, B
register
2com-32seg
3com-31seg
4com-30seg
5com-29seg
Q407
145
22-1
1
0
2com-36seg
3com-35seg
4com-34seg
5com-33seg
Q408
165
Bias
Voltage multiplying clock
Duty
Frame frequency
COM driver
SEG driver
Display control
Driver
2com-40seg
3com-39seg
4com-38seg
5com-37seg
Q409
185
SEG pin
Chapter 22 LCD Drivers
COM pin
Panel
LCD