ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 325

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.2.6 Display Allocation Register A (DS0C0A to DS39C4A)
Address: 0F400H to 0F427H, 0F440H to 0F467H, 0F480H to 0F4A7H, 0F4C0H to 0F4E7H, 0F500H to 0F527H
Access: R/W
Access size: 8-bit
Initial value: Undefined
DSmCnA (m= 0 to 39, n = 0 to 4) are special function registers (SFRs) that are used for the programmable display
allocation function.
Each valid bit of DSmCnA becomes undefined at system reset.
Table 22-3 shows a list of the display allocation register A.
[Description of Bits]
Initial value
DSmCnA
•
R/W
a5 to a0 (bit 5 to 0)
The a5 to a0 bits of DSmCnA (m = 0 to 39, n = 0 to 4) are used to select the addresses of the display registers
(DSPR00 to 27) that are output to common n of segment m.
Set DSmCnA when the DASN bit of the display mode register 1 (DSPMOD1) is “0”. When the DASN bit is
“1”, access from the CPU is invalid.
R/W
—
7
0
R/W
—
6
0
R/W
a5
5
0
22-13
R/W
a4
4
x
ML610Q407/ML610Q408/ML610Q409 User's Manual
R/W
a3
3
x
R/W
a2
2
x
Chapter 22 LCD Drivers
R/W
a1
1
x
R/W
a0
0
x