ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 181

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 12 Synchronous Serial Port
12.3 Description of Operation
12.3.1 Transmit Operation
Figure 12-3 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 0 (Negative Logic)
Figure 12-2 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 0 (Positive Logic)
Figure 12-4 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 (Positive Logic)
When “1” is written to the SnMD1 bit and "0" is written to the SnMD0 bit of the serial port mode register (SIOnMOD0),
this LSI is set to the transmit mode.
When transmitted data is written to the serial port transmit/receive buffer (SIOnBUFL, "H") and the SnEN bit of the
serial port control register (SIOnCON) is set to “1”, transmission starts. When transmission of 8/16-bit data terminates, a
synchronous serial port interrupt (SIOnINT) occurs and the SnEN bit is set to “0”.
The transmitted data is output from the Port 4's tertiary function (P42/SOUT0, P46/SOUT0) or from the Port 5's tertiary
function (P52/SOUT1, P56/SOUT1).
When an internal clock is selected in the serial port mode register (SIOnMOD1), the LSI is set to a master mode and
when an external clock (SCKn) is selected, the LSI is set to a slave mode.
The serial port mode register (SIOnMOD0) enables selection of MSB first/LSB first.
The transmitted data output pin (SOUTn) and the transfer clock input/output pin (SCKn) need to be set to the tertiary
function for the Port 4 or to the tertiary function for the Port 5.
The transmission operation waveforms of the synchronous serial port (8-bit length, LSB first) are shown in Figures 12-2
to 12-5, for the clock type 0 (positive logic), clock type 0 (negative logic), clock type 1 (positive logic), and clock type 1
(negative logic), respectively.
SIOnTRH,L
SIOnTRH,L
SIOnTRH,L
SIOnINT
SIOnINT
SIOnINT
SOUTn
SOUTn
SOUTn
SnEN
SCKn
SnEN
SCKn
SnEN
SCKn
0
0
0
(8-bit length, LSB first, n = 0, 1)
(8-bit length, LSB first, n = 0, 1)
(8-bit length, LSB first, n = 0, 1)
Transmitted data
Transmitted data
Transmitted data
1
1
1
2
2
2
12-10
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7