ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 90

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 6 Clock Generation Circuit
6.2.3 Frequency Control Register 1 (FCON1)
Address: 0F003H
Access: R/W
Access size: 8-bit
Initial value: 00H
FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
[Description of Bits]
Initial value
•
•
•
FCON1
R/W
SYSCLK (bit 0)
When the oscillation of high-speed clock is stopped (ENOSC bit = “0”), the SYSCLK bit is fixed to “0” and the
ENOSC (bit 1)
ENMLT (bit 2)
The SYSCLK bit is used to select system clock. It allows selection of the low-speed clock (LSCLK) or HSCLK
(1/nOSCLK: n = 1, 2, 4, 8) selected by using the high-speed clock frequency select bit (SYSC1, 0) of FCON0.
low-speed clock (LSCLK) is selected for system clock.
The ENOSC bit is used to select enable/disable of the oscillation of the high-speed clock oscillator circuit.
The ENMLT bit is used to select enable/disable of the operation of the low-speed double clock (LSCLK x 2).
SYSCLK
ENOSC
ENMLT
0
1
0
1
0
1
R/W
—
7
0
LSCLK (initial value)
HSCLK
Stops high-speed oscillation (initial value)
Enables high-speed oscillation
Disables low-speed double clock operation (initial value)
Enables low-speed double clock operation
R/W
—
6
0
R/W
—
5
0
6-4
R/W
—
4
0
Description
Description
Description
R/W
—
3
0
ENMLT
R/W
2
0
ENOSC
R/W
1
0
SYSCLK
R/W
0
0