DS26502L+ Maxim Integrated Products, DS26502L+ Datasheet - Page 21

• Manufacturer Part Number: DS26502L+
• Description: IC T1/E1/J1 64KCC ELEMENT 64LQFP
• Manufacturer: Maxim Integrated Products
• Type: BITS Elementr

Specifications of DS26502L+

• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -
• Output: -
• Input: -

4.5 JTAG
4.6 Line Interface
RRING
NAME
JTCLK
NAME
TRING
MCLK
JTRST
THZE
JTMS
JTDO
RTIP
JTDI
TTIP
TYPE
TYPE
O
O
O
I
I
I
I
I
I
I
I
JTAG Clock. This clock input is typically a low frequency (less than 10MHz)
50% duty cycle clock signal.
JTAG Mode Select (with Pullup). This input signal is used to control the
JTAG controller state machine and is sampled on the rising edge of JTCLK.
JTAG Data Input (with Pullup). This input signal is used to input data into
the register that is enabled by the JTAG controller state machine and is sampled
on the rising edge of JTCLK.
JTAG Data Output. This output signal is the output of an internal scan shift
register enabled by the JTAG controller state machine and is updated on the
falling edge of JTCLK. The pin is in the high-impedance mode when a register
is not selected or when the JTRST signal is high. The pin goes into and exits the
high impedance mode after the falling edge of JTCLK
JTAG Reset (Active Low). This input forces the JTAG controller logic into
the reset state and forces the JTDO pin into high impedance when low. This pin
should be low while power is applied and set high after the power is stable.
The pin can be driven high or low for normal operation, but must be high for
JTAG operation.
Master Clock Input. A (50ppm) clock source. This clock is used internally for
both clock/data recovery and for the jitter attenuator for both T1 and E1 modes.
The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When
using the DS26502 in T1-only operation, a 1.544MHz (50ppm) clock source
can be used.
Receive Tip. Analog input for clock recovery circuitry. This pin connects via a
1:1 transformer to the network. See the Line Interface Unit section for details.
Receive Ring. Analog input for clock recovery circuitry. This pin connects via
a 1:1 transformer to the network. See the Line Interface Unit section for details.
Transmit Tip. Analog line-driver output. This pin connects via a 1:2 step-up
transformer to the network. See the Line Interface Unit section for details.
Transmit Ring. Analog line-driver output. This pin connects via a 1:2 step-up
transformer to the network. See the Line Interface Unit section for details.
Transmit High-Impedance Enable. When high, TTIP and TRING will be
placed into a high-impedance state.
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FUNCTION
FUNCTION