DS26502L+ Maxim Integrated Products, DS26502L+ Datasheet - Page 36
DS26502L+
Manufacturer Part Number
DS26502L+
Description
IC T1/E1/J1 64KCC ELEMENT 64LQFP
Manufacturer
Maxim Integrated Products
Type
BITS Elementr
Datasheet
1.DS26502LN.pdf
(125 pages)
Specifications of DS26502L+
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency-max
-
Output
-
Input
-
- Current page: 36 of 125
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Note 1:
Note 2:
Bits 4 to 7: Transmit Mode Configuration (TMODE[3:0]). Used to select the operating mode of the transmit path for the
DS26502.
TMODE3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
The DS26502 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the
In addition to setting the TMODE bits to 6312kHz Synchronization Interface mode, the Transmit PLL must also be configured to
multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame
aligned to sync signal on the TS_8K_4 pin.
transmit a 6312kHz signal through the Transmit PLL Control Register (TPCR.6 and TPCR.7)
TMODE2
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
TMODE1
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
TMODE0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
T1 ESF (Note: In this mode the TFSE (T1TCR2.6) bit should be
36 of 125
64kHz + 8kHz + 400Hz Synchronization Interface
E1 G.703 2048 kHz Synchronization Interface
6312kHz Synchronization Interface (Note 2)
64kHz + 8kHz Synchronization Interface
Transmit Path Operating Mode
E1 CRC4 + CAS (Note 1)
E1 FAS + CAS (Note 1)
E1 CRC4
Reserved
Reserved
Reserved
Reserved
set = 0.)
E1 FAS
J1 ESF
T1 D4
J1 D4
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