DS26502L+ Maxim Integrated Products, DS26502L+ Datasheet - Page 74

• Manufacturer Part Number: DS26502L+
• Description: IC T1/E1/J1 64KCC ELEMENT 64LQFP
• Manufacturer: Maxim Integrated Products
• Type: BITS Elementr

Specifications of DS26502L+

• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -
• Output: -
• Input: -

12.2 Alternate Sa/Si Bit Access Based on Double-Frame
On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and
Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the
receive align frame bit in status register 4 (SR4.0) will indicate that the contents of the RAF and RNAF
have been updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers.
The host has 250µs to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the transmit
align frame bit in status register 4 (SR4.3). The host can use the SR4.3 bit to know when to update the
TAF and TNAF registers. It has 250µs to update the data or else the old data will be retransmitted. If the
TAF an TNAF registers are only being used to source the align frame and non-align frame-sync
patterns, then the host need only write once to these registers. Data for the Si bit can come from the Si
bits of the RAF and TNAF registers, the TSiAF and TSiNAF registers, or passed through from the TSER
pin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: Frame Alignment Signal Bit 0 (FAS0). In normal operation this bit will be = 1.
Bit 1: Frame Alignment Signal Bit 1 (FAS1). In normal operation this bit will be = 1.
Bit 2: Frame Alignment Signal Bit 2 (FAS2). In normal operation this bit will be = 0.
Bit 3: Frame Alignment Signal Bit 3 (FAS3). In normal operation this bit will be = 1.
Bit 4: Frame Alignment Signal Bit 4 (FAS4). In normal operation this bit will be = 1.
Bit 5: Frame Alignment Signal Bit 5 (FAS5). In normal operation this bit will be = 0.
Bit 6: Frame Alignment Signal Bit 6 (FAS6). In normal operation this bit will be = 0.
Bit 7: International Bit (Si)
Si
X
7
0
FAS6
RAF
Receive Align Frame Register
56h
X
6
0
FAS5
X
5
0
FAS4
X
4
0
74 of 125
FAS3
X
3
0
FAS2
X
2
0
FAS1
X
1
0
FAS0
X
0
0