PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 130

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.6.1
Access in demultiplexed P-interface mode:
4.6
Access in multiplexed P-interface mode:
Reset value: 00
Note: If EMOD:ECMD2 is set to ’0’ some restrictions apply to the setting of register
PMD1..0
PCR
Note: Only single clock rate is allowed in PCM-mode 2!
PSM
Semiconductor Group
bit 7
PMD1
PMOD (see chapter 4.5).
EPIC
PCM-Mode Register (PMOD)
PCM-Mode. Defines the actual number of PCM-ports, the data rate range
and the data rate stepping.
PMD1..0
00
01
10
11
The actual selection of physical pins is described below (AIS1/0).
PCM-Clock Rate.
0… single clock rate, data rate is identical with the clock frequency supplied
1… double clock rate, data rate is half the clock frequency supplied on pin
PCM Synchronization Mode.
A rising edge on PFS synchronizes the PCM-frame. PFS is not evaluated
directly but is sampled with PDC.
0… the external PFS is evaluated with the falling edge of PDC. The internal
1… the external PFS is evaluated with the rising edge of PDC. The internal
PMD0
®
-1
on pin PDC.
PDC.
PFS (internal frame start) occurs with the next rising edge of PDC.
PFS (internal frame start) occurs with this rising edge of PDC.
H
PCM-
Mode
0
1
2
3
PCR
PSM
Port
Count
4
2
1
2
130
AIS1
min.
256
512
1024
512
read/write
read/write
Detailed Register Description
Data Rate
AIS0
[kbBt/s]
max.
2048
4096
8192
4096
address: 10
address: 20
AIC1
PEB 20550
PEF 20550
Data Rate
Stepping
[kBit/s]
256
512
1024
512
bit 0
H
H
AIC0
01.96