PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 183

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

XCS2..1
4.7.23 Transmit Byte Count High (XBCH)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 0000xxxx
DMA
XC
Note: Only valid in DMA-mode.
XBC11..8 Transmit Byte Count high.
4.7.24 Time Slot Assignment Register Transmit (TSAX)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
TSNX5..0 Time Slot Number Transmit.
Semiconductor Group
bit 7
bit 7
TSNX5
DMA
DMA-mode.
Selects the data transfer mode between the SACCO FIFOs and the system
memory:
0…interrupt controlled data transfer (interrupt mode).
1…DMA controlled data transfer (DMA-mode).
Transmit Continuously.
When XC is set the SACCO continuously requests for transmit data ignoring
the transmit byte count programmed in register XBCH and XBCL.
Together with XBC7…XBC0 the length of the next frame to be transmitted in
DMA-mode is determined (1…4096 bytes).
Selects one of up to 64 time slots (00
clock mode 2. The number of bits per time slot is programmable in register
XCCR.
Transmit Clock Shift bit2-1.
Together with XCS0 in register CCR2 the transmit clock shift can be adjusted
in clock mode 2.
TSNX4
H
0
TSNX3
0
TSNX2
XC
183
TSNX1
XBC11
write
write
write
write
H
- 3F
address: (Ch-A/Ch-B): 2D
address: (Ch-A/Ch-B): 5A
address: (Ch-A/Ch-B): 30
address: (Ch-A/Ch-B): 60
H
Detailed Register Description
) in which data is transmitted in
XBC10
TSNX0
XBC9
XCS2
PEB 20550
PEF 20550
bit 0
bit 0
XBC8
XCS1
H
H
H
H
/70
/E0
/DA
/6D
01.96
H
H
H
H