PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 21

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Pin Definitions and Functions (cont’d)
SACCO-Interface
Pin No.
43
41
39
38
42
40
Semiconductor Group
Symbol
DRQRA
DRQRB
DRQTA
DRQTB
DACKA
DACKB
Input (I)
Output (O)
O
O
O
O
I
I
Function
DMA-Request Receiver Channel A/B
The receiver of HDLC-channel A/B requests a
DMA-data transfer by activating this lines. The
DRQR-pin remains "high" as long as the receiver
FIFO requires data transfers. Only blocks of 32,
16, 8 or 4 bytes are transferred.
DMA-Request Transmitter Channel A/B
The transmitter of HDLC-channel A/B requests a
DMA-data transfer by activating this lines. The
DRQT-pin remains "high" as long as the transmit
FIFO requires data transfers. The number of data
bytes to be transferred from system memory to the
FIFO must be written first into the XBCH, XBCL
registers (byte count registers).
DMA-Acknowledge HDLC-Channel A/B, active
low.
When "low", this lines notifies the HDLC-channel,
that the requested DMA-cycle is in progress.
Together with RD (DRQR) or WR(DRQT) DACK
works like CS to enable a read or write operation
to the top of the receive or the transmit FIFO.
When DACK is active, the address lines are
ignored and the FIFOs are implicitly selected.
When DACK is not used it has to be connected to
V
DD
.
21
PEB 20550
PEF 20550
Overview
01.96