PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 298

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

address in order to be transmitted in the subsequent odd CFI timeslot!
In upstream direction a change detection mechanism is active to search for changes in
the received C/I or SIG values. Upon a change, the address of the involved subscriber
is stored in a 9 byte deep FIFO (CIFIFO) and an interrupt (ISTA:SFI) is generated. The
C/I or SIG value out of the Control Memory. The address FIFO serves to increase the
latency time for the P to react to SFI interrupts. If several C/I or SIG changes occur
before the P executes the SFI interrupt handling routine, the addresses of the first
9 changes are stored in the CIFIFO and the corresponding C/I or SIG values are stored
in the control memory (CM). If more than 9 changes occur before the P reads the
CIFIFO, these additional changes are no longer updated in the control memory. This is
to prevent any loss of change information. These additional changes remain pending at
the serial interface. As soon as the P reads the CIFIFO, and thus, empties locations of
the FIFO, these pending changes are sequentially written to the CM and the
corresponding addresses to the FIFO. It is thus ensured that no change information is
lost even if, for example, all 32 subscribers simultaneously generate a change in their C/
I or SIG channel!
CFI timeslots which should be processed by the CS handler must first be initialized as
MF/CS channels with appropriate codes in the Control Memory code field (refer to
chapter 5.5.1).
5.5.2
If the configurable interface (CFI) of the ELIC is operated as IOM or SLD interface, it is
necessary to communicate with the connected subscriber circuits such as layer-1
transceivers (ISDN line cards) or codec filter devices (analog line cards) over the
Command/Indication (C/I) or the signaling (SIG) channel. In order to simplify this task the
ELIC has implemented the Control/Signaling Handler (CS Handler).
In downstream direction, the 4, 6 or 8 bit C/I or SIG value can simply be written to the
Control Memory data field which will then be repeatedly transmitted in every frame to the
subscriber circuit until a new value is loaded.
Note that the downstream C/I or SIG value must always be written to the even CM
Semiconductor Group
P can then first determine the CM address by reading the FIFO before reading the new
Control/Signaling (CS) Handler
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Application Hints
PEB 20550
PEF 20550
01.96