PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 358

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.1.2.3 Basic D-Channel Arbiter Initialization
Write
6.1.2.4 SACCO-B Initialization
Initialization of SACCO-B for communication, via the PCM highway, with the (non-PBC)
group controller:
Write
Write
Write
Write
Write
Write
Write
Write
Write
Reset SACCO-B:
Write
Read
Semiconductor Group
AMO
MODE = 48
TSAX = 0B
TSAR = 0B
XCCR = 07
RCCR = 07
RAL1 = 09
RAL2 = FE
CCR2 = 38
CCR1 = 9E
CMDR = C1
ISTA_B= 10
= 69
H
H
H
H
H
H
H
H
H
H
H
H
full selection counter set to general worst case delay of
14 frames; suspend counter active; arbiter control via
C/I channel; control channel activated
8 bit non-auto mode; continuous frame transmission OFF;
HDLC receiver active; test loop disabled
assign transmit time slot 3: set XCS bits to shift output
window to time slot 1, set TSNX1 bit to delay the output
window by 2 time slots
assign receive time slot 3: set RCS bits to shift input window
to time slot 1, set TSNR1 bit to delay the input window by
2 time slots
8 bits transmitted per output window
8 bits received per input window
receive address
broadcast receive address
set XCS and RCS bits (see TSAX, TSAR); enable TxDB pin
power up; point-to-point configuration; push-pull output;
FLAGs as interframe time fill; double-rate data clock;
clock mode 2
RMC; RHR; XRES
transmit pool ready
358
Application Notes
PEB 20550
PEF 20550
01.96